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Host-driven execution of applications on modern GPU-accelerated systems suffer from frequent host-device synchronizations, data movement and limited flexibility in scheduling user tasks. We present CharminG, a runtime system designed to run entirely on the GPU without any interaction with the host. CharminG takes inspiration from the Charm++ parallel programming system and implements processor virtualization and message-driven execution on the GPU. We evaluate the composability and preliminary performance of CharminG with a proxy application that performs the Jacobi iterative method in a two-dimensional grid, using the Lassen supercomputer at Lawrence Livermore National Laboratory.

In this paper, a model-driven software collaborative modeling method is proposed, and a software collaborative modeling framework on model assembly and model updating is established. The composability of models, the integrity of model assembly and the consistency of model updating are studied from two aspects: model assembly mechanism and model updating mechanism. The collaborative modeling protocol is defined, and six collaborative relationship stereotypes are introduced to add collaborative semantics to the model based on the extensible mechanism of UML. The algorithm of model assembly and integrity checking is proposed and the collaborative modeling of multiple clients is implemented. The algorithm of model updating and consistency checking is proposed to solve the problem of model updating in collaborative modeling.

Over the last few years, we have experienced a massive transformation of the Software Defined Networking ecosystem with the development of SDNEnhancements, e.g., Statesman, ESPRES, Pane, and Pyretic, to provide better composability, better utilization of TCAM, consistent network updates, or congestion free updates. The end-result of this organic evolution is a disconnect between the SDN applications and the data-plane. A disconnect which can impact an SDN application's performance and efficacy. In this paper, we present the first systematic study of the interactions between SDNEnhancements and SDN applications -- we show that an SDN application's performance can be significantly impacted by these SDNEnhancements: for example, we observed that the efficiency of a traffic engineering SDN application was reduced by 24.8%. Motivated by these insights, we present, Mozart, a redesigned SDN controller centered around mitigating and reducing the impact of these SDNEnhancements. Using two prototypes interoperating with seven SDN applications and two SDNEnhancements, we demonstrate that our abstractions require minimal changes and can restore an SDN application's performance. We analyzed Mozart's scalability and overhead using large scale simulations of modern cloud networks and observed them to be negligible.

Programmers, researchers, system administrators, and data scientists often build complex workflows based on command-line applications. To give these power users the well-known benefits of GUIs, we created Bespoke, a system that synthesizes custom GUIs by observing user demonstrations of command-line apps. Bespoke unifies the two main forms of desktop human-computer interaction (command-line and GUI) via a hybrid approach that combines the flexibility and composability of the command line with the usability and discoverability of GUIs. To assess the versatility of Bespoke, we ran an open-ended study where participants used it to create their own GUIs in domains that personally motivated them. They made a diverse set of GUIs for use cases such as cloud computing management, machine learning prototyping, lecture video transcription, integrated circuit design, remote code deployment, and gaming server management. Participants reported that the benefit of these bespoke GUIs was that they exposed only the most relevant subset of options required for their specific needs. In contrast, vendor-made GUIs usually include far more panes, menus, and settings since they must accommodate a wider range of use cases.

With the rise of ever-more sophisticated wearables and sensing technologies, mobile health continues to be an active area of research. However, from a clinical researcher point of view, testing novel use of the mobile health innovations remains a major hurdle, as composing a clinical trial using a combination of technologies still remains in the realm of computer scientists. We take a software-inspired viewpoint of clinical trial designs to design, develop and validate HealthSense to enable expressibility of complex ideas, composability with diverse devices and services while maximally maintaining simplicity for a clinical research user. A key innovation in HealthSense is the concept of a study state manager (SSM) that modifies parameters of the study over time as data accumulates and can trigger external events that affect the participant; this design allows us to implement nearly arbitrary clinical trial designs. The SSM can funnel data streams to custom or third-party cloud processing pipelines and the result can be used to give interventions and modify parameters of the study. HealthSense supports both Android and iOS platforms and is secure, scalable and fully operational. We outline three trials (two with clinical populations) to highlight simplicity, composability, and expressibility of HealthSense.

Generating good random values described by algebraic data types is often quite intricate. State-of-the-art tools for synthesizing random generators serve the valuable purpose of helping with this task, while providing different levels of invariants imposed over the generated values. However, they are often not built for composability nor extensibility, a useful feature when the shape of our random data needs to be adapted while testing different properties or sub-systems. In this work, we develop an extensible framework for deriving compositional generators, which can be easily combined in different ways in order to fit developers' demands using a simple type-level description language. Our framework relies on familiar ideas from the a la Carte technique for writing composable interpreters in Haskell. In particular, we adapt this technique with the machinery required in the scope of random generation, showing how concepts like generation frequency or terminal constructions can also be expressed in the same type-level fashion. We provide an implementation of our ideas, and evaluate its performance using real-world examples.

We revisit the gap between what distributed systems need from the transport layer and what protocols in wide deployment provide. Such a gap complicates the implementation of distributed systems and impacts their performance. We introduce Tunable Multicast Communication (TMC), an abstraction that allows developers to easily specialize communication channels in distributed systems. TMC is presented as a deployable and extensible user-space library that exposes high-level tunable guarantees. TMC has the potential of improving the performance of distributed applications with minimal-to-zero development and deployment effort.

Hybrid practices are emerging that integrate creative materials like paint, clay, and cloth with intangible immaterials like computation, electricity, and heat. This work aims to expand the design potential of immaterial elements by transforming them into manipulatable, observable and intuitive materials. We explore one such immaterial, electric heat, and develop a maker-friendly fabrication pipeline and crafting support tool that allows users to experientially compose resistive heaters that generate heat spatially and temporally. These heaters are then used to couple heat and thermoreactive materials in a class of artifacts we term Thermoreactive Composites (TrCs). In a formal user study, we observe how designing fabrication workflows along dimensions of composability and perceivability better matches the working styles of material practitioners without domain knowledge of electronics. Through exemplar artifacts, we demonstrate the potential of heat as a creative material and discuss implications for immaterials used within creative practices.

Convolutional Neural Networks (CNN) are widely used for Deep Learning tasks. CNN pruning is an important method to adapt a large CNN model trained on general datasets to fit a more specialized task or a smaller device. The key challenge is on deciding which filters to remove in order to maximize the quality of the pruned networks while satisfying the constraints. It is time-consuming due to the enormous configuration space and the slowness of CNN training. The problem has drawn many efforts from the machine learning field, which try to reduce the set of network configurations to explore. This work tackles the problem distinctively from a programming systems perspective, trying to speed up the evaluations of the remaining configurations through computation reuse via a compiler-based framework. We empirically uncover the existence of composability in the training of a collection of pruned CNN models, and point out the opportunities for computation reuse. We then propose composability-based CNN pruning, and design a compression-based algorithm to efficiently identify the set of CNN layers to pre-train for maximizing their reuse benefits in CNN pruning. We further develop a compiler-based framework named Wootz, which, for an arbitrary CNN, automatically generates code that builds a Teacher-Student scheme to materialize composability-based pruning. Experiments show that network pruning enabled by Wootz shortens the state-of-art pruning process by up to 186X while producing significantly better pruning results.

Unexpectedly, the rise of serverless computing has also collaterally started the "democratization" of massive-scale data parallelism. This new trend heralded by PyWren pursues to enable untrained users to execute single-machine code in the cloud at massive scale through platforms like AWS Lambda. Inspired by this vision, this industry paper presents IBM-PyWren, which continues the pioneering work begun by PyWren in this field. It must be noted that IBM-PyWren is not, however, just a mere reimplementation of PyWren's API atop IBM Cloud Functions. Rather, it is must be viewed as an advanced extension of PyWren to run broader MapReduce jobs. We describe the design, innovative features (API extensions, data discovering & partitioning, composability, etc.) and performance of IBM-PyWren, along with the challenges encountered during its implementation.

Computer Generated Forces (CGF) behavior modeling technology is the core of the CGF modeling technology, it can make the CGF entities show a certain degree of human behavior characteristics, with varying degrees of autonomy, reasoning ability and adaptability. However, the current CGF behavior modeling methods are difficult to reflect the reusability of the behavior model, result in the workload of behavior modeling become very heavy. To solve this problem, this paper proposes a reusable behavior modeling method based on atom action and atom condition: by means of combining atom actions into the State, connecting the States by atom condition groups to form Doctrine, and designing XML (Extensible Markup Language) template file for State and Doctrine, we can realize the modeling, representation and storage of CGF behavior. Research shows that this method has good reusability, composability and extendibility, which can reduce the workload of behavior modeling.

The last few years have seen a massive and organic transformation of the Software Defined Networking ecosystem with the development of enhancements, e.g., Statesman, ESPRES, PANE, and Athens, to provide better composability, better utilization of TCAM, consistent network updates, or congestion free updates. The end-result of this organic evolution is a disconnect between the SDN applications and the dataplane. A disconnect which can impact an SDN application's performance or correctness.In this paper, we present the first systematic study of the interactions between enhancements and SDN applications -- we show that an application's performance can be significantly impacted by these enhancements: with the efficiency of a traffic engineering App reduced by 24.8%. Motivated by these insights, we argue for a redesign of the SDN controller centered around mitigating and reducing the impact of these enhancements. We demonstrate through an initial prototype and with experiments that our abstractions require minimal changes and can restore an SDN application's performance and efficiency.

A recent trend in application development for the web is a move towards rich internet applications (RIAs). As more and more of the application logic is moved to the client, RIAs can benefit from concurrency in order to increase overall performance as well as responsiveness of the application. Additionally, RIAs are often written in an event-driven style of programming to react to incoming events of a multitude of services that are integrated within the application. In this paper we argue that, while individual technologies exist to tackle both concerns, these technologies cannot easily be integrated in an ad hoc way. To increase the modularisability and composability of RIAs we propose a new programming model based on actors and reactors that encapsulate different parts of the application. We show that our model is able to exploit some of the available concurrency while reducing the required amount of event-driven code. Both actors and reactors are modular components that can be glued together via a unified communication mechanism. We evaluate our approach by means of a motivating example of a collaborative code editor.

Microservices are replacing monolithic applications by splitting them out into small and independent artifacts that collaborate with one another. Focused on managing highly cohesive information, microservices may be composed to provide richer and linked information. This paper presents a composition method, aimed at composing semantic microservices for achieving data integration based on Linked Data principles. Moreover, the proposed method leverages the independence of development and composability of microservices. This paper also presents a framework and a case study for the proposed method.

The reactor model is a foundational programming model for distributed computing, whose focus is modularizing and composing computations and message protocols. Previous work on reactors dealt mainly with the programming model and its composability properties, but did not show how to schedule computations in reactor-based programs. In this paper, we propose a pluggable scheduling algorithm for the reactor model. The algorithm is customizable with user-defined scheduling policies. We define and prove safety and progress properties. We compare our implementation against the Akka actor framework, and show up to 3× performance improvements on standard actor benchmarks.

We believe that programming is mainly a linguistic process concerning the development of the language abstractions better suited to deal with a given problem domain. The main responsibility of a linguistic system is to capture and incorporate the knowledge of domain experts, while trying to minimize the meta level efforts, thus allowing users to concentrate on modeling activities. While a meta level is necessary in order to write instances, it is possible to define a generic meta level capable of representing any specific entity. We introduce an instance modeling language, Entities, combining a rich graphical notation, an optionally typed structure, and composability with other domain specific languages. The visual expressivity is comparable to a mindmapping tool, and makes it best suited for knowledge representation domains. The optional typing enables an exploratory, bottom up approach to metamodeling. The composability with strictly typed languages makes modeling a much more flexible experience.

The definition of a projectional editor does not just specify the notation of a language, but also how users interact with the notation. Because of that it is easy to end up with different interaction styles within one and between multiple languages. The resulting inconsistencies have proven to be a major usability problem. To address this problem, we introduce grammar cells, an approach for declaratively specifying textual notations and their interactions for projectional editors. In the paper we motivate the problem, give a formal definition of grammar cells, and define their mapping to low-level editor behaviors. Our evaluation based on project experience shows that grammar cells improve editing experience by providing a consistent and intuitive ``text editor-like'' user experience for textual notations. At the same time they do not limit language composability and the use of non-textual notations, the primary benefits of projectional editors. We have implemented grammar cells for Jetbrains MPS, but they can also be used with other projectional editors.

Synthetic biology aims to create functional devices, systems, and organisms with novel and useful functions taking advantage of engineering principles applied to biology. Despite great progress over the last decade, an underlying problem in synthetic biology remains the limited number of high-performance, modular, composable parts. A potential route to solve parts bottleneck problem in synthetic biology utilizes the programmability of nucleic acids inspired by molecular programming approaches that have demonstrated complex biomolecular circuits evaluating logic expressions in test tubes.Using a library of de-novo-designed toehold switches with orthogonality and modular composability, we demonstrate how toehold switches can be incorporated into decision-making RNA networks termed ribocomputing devices to rapidly evaluate complex logic in living cells. We have successfully demonstrated a 4-input AND gate, a 6-input OR gate, and a 12-input expression in disjunctive normal form in E. coli. The compact encoding of ribocomputing system using a library of modular parts is amenable to aggressive scale-up towards complex control of in vivo circuitry towards autonomous behaviors and biomedical applications.

This paper introduces versioned programming, a technique that can be used to convert pointer-based data structures into efficient, lock-free implementations. Versioned programming allows arbitrary composition of pointer modifications. Taking linked-lists as an example, VLISTs, or versioned lists, support features missing in other lock-free implementations, such as double linking and atomic moves among lists.The main idea of versioning is to allow different versions of a nodes exist at the same time such that each thread can pick the appropriate version and has a consistent view of the whole data structure. We present a detailed example of VLISTs, simple enough to include all code inline. The paper also evaluates versioned tree implementations.We evaluate versioned programming against several concurrency techniques. With a modest number of writers, versioned programming outperforms read-log-update, which locks nodes. VLIST out-perform lists with SwissTM, a highquality STM, showing the value of trading some programmer-transparency for performance. Composability hurts performance compared to a non-composable, hand-written lock-free algorithm. Using the technique described in this paper, application developers can have both the performance scalability of sophisticated synchronization techniques with functionality and simplicity comparable to coarse locks.

Source code in software systems has been shown to have a good degree of repetitiveness at the lexical, syntactical, and API usage levels. This paper presents a large-scale study on the repetitiveness, containment, and composability of source code at the semantic level. We collected a large dataset consisting of 9,224 Java projects with 2.79M class files, 17.54M methods with 187M SLOCs. For each method in a project, we build the program dependency graph (PDG) to represent a routine, and compare PDGs with one another as well as the subgraphs within them. We found that within a project, 12.1% of the routines are repeated, and most of them repeat from 2–7 times. As entirety, the routines are quite project-specific with only 3.3% of them exactly repeating in 1–4 other projects with at most 8 times. We also found that 26.1% and 7.27% of the routines are contained in other routine(s), i.e., implemented as part of other routine(s) elsewhere within a project and in other projects, respectively. Except for trivial routines, their repetitiveness and containment is independent of their complexity. Defining a subroutine via a per-variable slicing subgraph in a PDG, we found that 14.3% of all routines have all of their subroutines repeated. A high percentage of subroutines in a routine can be found/reused elsewhere. We collected 8,764,971 unique subroutines (with 323,564 unique JDK subroutines) as basic units for code searching/synthesis. We also provide practical implications of our findings to automated tools.

The automatic User Interface (UI) composition of UI components thanks to UI composition operators (composers) is one of the approaches to improve the UI development, to produce adaptive UI and to master the development of large scale UI. In this setting, the verification concern of UI component composition is still a challenge. This work addresses the composability of components and their services depending on proposed UI composition operators defined according to standard abstraction levels. The main contributions of this paper are a component model to carry on a containing UI composition, the identification of the main aspects of the UI composition, the proposition of some new UI composers including semantic and temporal aspects and the checking of composability properties of composers to verify the correctness of the UI composition.

Many indoor localization algorithms have been proposed to enable location-based applications in indoor environments. However, these systems are monolithic and not component-based. We present BearLoc, a distributed modular framework for indoor localization systems that provides (1) natural development abstractions for sensor, algorithm, and application components, and (2) easy and flexible component composition. We demonstrate the merits of BearLoc with an example use case. Our evaluation shows we can reduce developer lines of code by 60% while introducing acceptable network delay overhead.

In singlecore processors timing analysis involves a step of Execution Time Analysis at task level that yields an Execution Time Bound (ETB) for the task, and one of schedulability analysis, where the scheduling attributes of the individual tasks, including the ETB, are studied from a system level perspective. Response Time Analysis serves as a compositional bridge between those two steps by accounting for the contention that arises from resource sharing. In this paper, we show that the advent of multicore processors challenges the viability of this two-step approach. This stems from the fact that inter-task interference effects in a multicore are much more intricate in nature than what can be compositionally captured in response time analysis by widening the tasks' ETB with the time intervals during which tasks cannot progress while actually holding the CPU; we also show how contention in the access to hardware shared resources creates a circular dependence between the task ETB and its actual scheduling at run time. Finally, we show how various degrees of time composability can help breaking this knot.

Stencils occur in many areas, but they are ubiquitous in scientific computing. They range from the simple Jacobi iterations to the extremely complex ones used in the solution of highly nonlinear partial differential equations (PDE). High level programming languages typically used in implementation of scientific software, by not providing explicit support for stencils, force each implementation to make choices about expressing its specifics such as dimensionality, data layout, order of access and order of operations. These choices often hide the opportunity for optimizations from the compilers. Therehave been attempts to provide abstractions for simpler stencils, and they have met with success in some areas, but multiphysics scientific applications present challenges that cannot be met by simple stencil abstractions. The applications may have hierarchy, or non-uniformity, or both in their discretizations which cannot be expressed by stencils describing uniform discretizations. The physics operators being applied maybe non-linear which would demand composability of stencils. As the order of the solution method increases, the size and the reach of stencil also increases, and there may be conditions that imply the application of the stencil to an arbitrary subset of the discretized points. And finally, if there are multiple steps involved in an update, intermediate results need to be managed. AMR Shift Calculus, (Phil Colella and Brian Van Straalen 2014), provides a generalized abstraction that addresses many of these concerns. It provides a means of expressing stencil computations in the form of a collection of shift operations combined with associated weights, that can be applied to a specified collection of discretized points. The shift calculus also addresses the hierarchy in the discretization, and defines operators on stencils that allow more complex stencils to be composed from simpler ones. Because the shift calculus makes it possible to express the computation concisely and precisely, it gets around the problem of false dependencies. Additionally, the composability of the stencil operators exposes possibilities of loop or even function fusion, and the granularity for holding intermediate values to the compiler for better optimization opportunities.The included slide presentation is organized in five sections. The first section gives examples of discretization from simple Poisson to complex compressible Navier-Stokes (CNS) equations and addresses thelevel of abstraction needed to express the computations on these discretizations. The second section outlines several challenges that are unique to scientific applications, and the ways in which many abstractions that have proved useful elsewhere fail to work with scientific computing. The third section goes on to describe the AMR shift calculus with emphasis on features that are typically not found in other approaches to stencils based abstractions, but are necessary for the solving complex PDE's in scientific computing. The fourth section provides an example of applying one aspect of the shift calculus to a CNS solver implemented in F90. The example replaces loop-nests that explicitly implement the first and second derivative operators being applied to various field variables in the solver. It not only collapses the line-count in the code, but also removes unnecessary specificity of the order of floating point operations in the implementation. Finally, the fifth section talks about the opportunities that are made available to compilers for optimizations by expressing the computations in a high level abstraction.

Integrated Modular Avionics (IMA) enables incremental qualification by encapsulating avionics applications into software partitions (SWPs), as defined by the ARINC 653 standard. SWPs, when running on top of single-core processors, provide robust time partitioning as a means to isolate SWPs timing behavior from each other. However, when moving towards parallel execution in many-core processors, the simultaneous accesses to shared hardware and software resources influence the timing behavior of SWPs, defying the purpose of time partitioning to provide isolation among applications. In this paper, we extend the concept of SWP by introducing parallel software partitions (pSWP) specification that describes the behavior of SWPs required when running in a many-core to enable incremental qualification. pSWP are supported by a new hardware feature called guaranteed resource partition (GRP) that defines an execution environment in which SWPs run and that controls interferences in the accesses to shared hardware resources among SWPs such that time composability can be guaranteed.

The significant increase in complexity of Exascale platforms due to energy-constrained, billion-way parallelism, with major changes to processor and memory architecture, requires new energy-efficient and resilient programming techniques that are portable across multiple future generations of machines. We believe that guaranteeing adequate scalability, programmability, performance portability, resilience, and energy efficiency requires a fundamentally new approach, combined with a transition path for existing scientific applications, to fully explore the rewards of todays and tomorrows systems. We present HPX -- a parallel runtime system which extends the C++11/14 standard to facilitate distributed operations, enable fine-grained constraint based parallelism, and support runtime adaptive resource management. This provides a widely accepted API enabling programmability, composability and performance portability of user applications. By employing a global address space, we seamlessly augment the standard to apply to a distributed case. We present HPX's architecture, design decisions, and results selected from a diverse set of application runs showing superior performance, scalability, and efficiency over conventional practice.

AUTOSAR is a standard framework that aims to address many software challenges such as composability, reusability and interoperability during automotive system development. To overcome these challenges, its specifications provide a basic infrastructure for software architecture, application interfaces, and development methodology, but still leave many detailed design decisions to developers such as runnable-to-task mapping and task priority assignment. Although these design decisions have a significant impact on the overall system performance, they have not been sufficiently addressed in the AUTOSAR standard framework. In this paper, we attempt to solve the priority assignment problem for AUTOSAR tasks and in-vehicle network messages. To do so, we first describe a real-time task chain model for AUTOSAR that is amenable to schedulability analysis, and then present a genetic priority assignment algorithm that can find near optimal solutions in a moderate amount of time. Our experiments show that the proposed algorithm outperforms existing methods, producing 6% better schedulable solutions than HOPA [4] and running 18 times faster than PGA [5].

In highly configurable systems the configuration space is too big for (re-)certifying every configuration in isolation. In this project, we combine software analysis with network analysis to detect which configuration options interact and which have local effects. Instead of analyzing a system as Linux and SELinux for every combination of configuration settings one by one (>102000 even considering compile-time configurations only), we analyze the effect of each configuration option once for the entire configuration space. The analysis will guide us to designs separating interacting configuration options in a core system and isolating orthogonal and less trusted configuration options from this core.

Designing a SoC for applications with mixed time-criticality is a complex and time-consuming task. Even when SoCs are built from components with known real-time properties, they still have to be combined and configured correctly to assert that these properties hold for the complete system, which is non trivial. Furthermore, applications need to be mapped to the available hardware resources and correctly integrated with the SoC's software stack, such that the realtime requirements of the applications are guaranteed to be satisfied. However, as systems grow in complexity, the design and verification effort increases, which makes it difficult to satisfy the tight time-to-market constraint. Design tools are essential to speed up the development process and increase profit. This paper presents the design flow for the CompSOC FPGA platform: a template for SoCs with mixed time-criticality applications. This work outlines how the development time of such a platform instance is reduced by means of its comprehensive tool flow, that aids a system designer in creating hardware, the associated software stack, and application mapping. Copyright 2013 ACM.

Domain-specific languages improve ease-of-use, expressiveness and verifiability, but defining and using different DSLs within a single application remains difficult. We introduce an approach for embedded DSLs where 1) whitespace delimits DSL-governed blocks, and 2) the parsing and type checking phases occur in tandem so that the expected type of the block determines which domain-specific parser governs that block. We argue that this approach occupies a sweet spot, providing high expressiveness and ease-of-use while maintaining safe composability. We introduce the design, provide examples and describe an ongoing implementation of this strategy in the Wyvern programming language. We also discuss how a more conventional keyword-directed strategy for parsing of DSLs can arise as a special case of this type-directed strategy.

In this paper, we propose a mechanism of user-defined operators with better expressiveness while keeping composability. Our user-defined operators, named protean operators, can express arbitrary Parsing Expression Grammar (PEG) syntax, and they can also express complex user-defined literals. A library of user-defined operators is composable - the library can use with any other libraries. We have developed ProteaJ, which is an extension of Java 1.4 supporting protean operators.

State-of-the-art approaches to the development and analysis of real-time embedded systems assume seamless composition of the functional and timing behaviour of the distinct applications that compose the system. Unfortunately, the sharing of complex and stateful hardware resources is a serious threat to time composability: the dependences produced by their history of use cannot always be accurately accounted for by state-of-the-art timing analysis techniques. More recently, the attention paid to the contribution that the Real-Time Operating System (RTOS) can make to achieving -- or breaking -- time composability has grown. In this paper we present and experimentally evaluate a proof-of-concept implementation of a time-composable RTOS design concept in the specific incarnation as an ARINC-compliant partitioned system for avionics applications.

Pervasive health applications that compose longitudinal information streams to infer people's health and encourage lifestyle changes have the potential to substantially benefit public health. Off-the-shelf medical and wellness sensors meet the sensing requirements of such applications but their closed and vertically-integrated designs impede composability and complicate unified management. Furthermore, the lack of security and privacy controls discourages individuals from sharing their data. This paper presents HealthOS, a development and execution framework for pervasive health applications. HealthOS addresses the sensor and system incompatibility challenge through a set of adapters. Moreover, pipeline modules translate custom formats and protocols to the requirements of target applications/systems. These modules execute in HealthOS servers, programmable devices that expose Representational State Transfer (REST) interfaces for data retrieval and sensor management. HealthOS servers can store data locally or push them to untrusted, third party services. Finally, HealthOS leverages attribute-based encryption to offer sophisticated role-based and content-based access controls for users' data.

This paper presents Poli-C, a language extension, runtime library, and system daemon enabling fine-grained, language-level, hierarchical resource management policies. Poli-C is suitable for use in applications that compose parallel libraries, frameworks, and programs. In particular, we have added a powerful new statement to C for expressing resource limits and guarantees in such a way that programmers can set resource management policies even when the source code of parallel libraries and frameworks is not available. Poli-C enables application programmers to manage any resource exposed by the underlying OS, for example cores or IO bandwidth. Additionally, we have developed a domain-specific language for defining high-level resource management policies, and a facility for extending the kinds of resources that can be managed with our language extension. Finally, through a number of useful variations, our design offers a high degree of composability. We evaluate Poli-C by way of three case-studies: a scientific application, an image processing webserver, and a pair of parallel database join implementations. We found that using Poli-C yields efficiency gains that require the addition of only a few lines of code to applications.

We introduce a statically-typed language extensibility mechanism called active type-checking and translation (AT&T) that aims toward expressiveness, safety and composability. This mechanism allows users to equip type definitions with type-level functions that control the compilation process directly, at points that are relevant to that type's semantics.

As different workloads require different processor resources for better execution efficiency, recent work has proposed composable chip multiprocessors (CCMPs), which provide the capability to configure different number and types of processing cores at system runtime. However, such composable architecture poses a new significant challenge to system scheduler, that is, how to ensure priority-based performance for each task (i.e. fairness), while exploiting the benefits of composability by dynamically changing the hardware configurations to match the parallelism requirements in running tasks (i.e. resource allocation). Current multicore schedulers fail to address this problem, as they traditionally assume fixed number and types of cores.In this work, we introduce centralized run queue (CRQ) and propose an efficiency-based algorithm to address the fair scheduling problem on CCMP. Firstly, instead of using distributed per-core run queues, this paper employs CRQ to simplify the scheduling and resource allocation decisions on CCMP, and proposes a pipeline-like scheduling mechanism to hide the large scheduling decision overhead on the centralized queue. Secondly, an efficiency-based dynamic priority (EDP) algorithm is proposed to keep fair scheduling on CCMP, which can not only provide homogenous tasks with performance proportional to their priorities, but also ensure equal-priority heterogeneous tasks to get equivalent performance slowdowns when running simultaneously. To evaluate our design, experimental studies are carried out to compare EDP on CCMP with several state-of-art fair schedulers on symmetric and asymmetric CMPs. Our simulation results demonstrate that, while providing good fairness, EDP on CCMP outperforms the best performing fair scheduler on fixed symmetric and asymmetric CMPs by as much as 11.8% in user-oriented performance, and by 12.5% in system throughput.

The paper presents a novel ecosystem for software-intensive embedded systems as an alternative to integration-centric software development. A set of necessary qualities is identified for the embedded platform enabling the ecosystem, i.e. deployability of new functions, maintainability over time, and configurability according to hardware within the product family. The embedded platform must support composability of software from different development stakeholders, such as the original equipment manufacturer, strategic and 3rd-party developers.The paper presents some key mechanisms for implementing the necessary certification in the platform that facilitates composability while still preserving dependability. A theoretical example of how this would look like in the automotive domain is presented, and an actual case of an in-vehicle platform implementing some of the mechanisms is shown.

Memory caches significantly improve the performance of workloads that have temporal and spatial locality by providing faster access to data. Current processor designs have multiple cores sharing a cache. To accurately model a workload performance and to improve system throughput by intelligently scheduling workloads on cores, we need to understand how sharing caches between workloads affects their data accesses.Past research has developed analytical models that estimate the cache behavior for combined workloads given the stack distance profiles describing these workloads. We extend this research by presenting an analytical model with contributions to accuracy and composability - our model makes fewer simplifying assumptions than earlier models, and its output is in the same format as its input, which is an important property for hierarchical composition during software performance modeling.To compare the accuracy of our analytical model with earlier models, we attempted to reproduce the reported accuracy of those models. This proved to be difficult. We provide additional insight into the major factors that influence analytical model accuracy.

The notion of representation systems describes structures that are algebraically closed under queries. It has recently been realized that representation systems are highly relevant also in the context of data exchange. We extend the notion of representation system to encompass data exchange mappings and their composition. Seen through this lens, two major classes of representation systems emerge, namely homomorphic data exchange systems and strong data exchange systems. The homomorphic "OWA" systems encompass the "classical" part of data exchange. Reasoning is modulo homomorphic equivalence (CQ-equivalence), and only unions of conjunctive queries and monotone data exchange mappings are supported.We then develop some new technical tools that allow us to prove that there is a class of '"CWA" strong representation systems in which reasoning is modulo isomorphic equivalence. These systems are based on conditional tables, and they support first order queries and non-monotonic data exchange mappings specified by a large class of second order dependencies. We achieve this by showing that, under a CWA-interpretation, conditional tables are chaseable with the aforementioned class of second order dependencies, and that the class is closed under composition in the CWA-setting.We also introduce a stricter notion of composability, and show that the class of (first order) source-to-target tuple generating dependencies is closed under the stricter notion of composability.

Date of Conference: 16 - 20 July 2012 Conference name: Proceedings of the 6th ACM International Conference on Distributed Event-Based Systems, DEBS'12 Data stream processing applications are often expressed as data flow graphs, composed of operators connected via streams. This structured representation provides a simple yet powerful paradigm for building large-scale, distributed, high-performance applications. However, there are many tasks that require sharing data across operators, and across operators and the runtime using a less structured mechanism than point-to-point data flows. Examples include updating control variables, sending notifications, collecting metrics, building collective models, etc. In this paper we describe CAPSULE, which fills this gap. CAPSULE is a code generation and runtime framework that offers an easy to use and highly flexible framework for developers to realize shared variables (CAPSULE term for shared state) by specifying a data structure (at the programming-language level), and a few associated configuration parameters that qualify the expected usage scenario. Besides the easy of use and flexibility, CAPSULE offers the following important benefits: (1) Custom Code Generation - CAPSULE makes use of user-specified configuration parameters and information from the runtime to generate shared variable servers that are tailored for the specific usage scenario, (2) Composability - CAPSULE supports deployment time composition of the shared variable servers to achieve desired levels of scalability, performance and fault-tolerance, and (3) Extensibility - CAPSULE provides simple interfaces for extending the CAPSULE framework with more protocols, transports, caching mechanisms, etc. We describe the motivation for CAPSULE and its design, report on its implementation status, and then present experimental results. Copyright © 2012 ACM.

In this paper, we perform a study of unifying two design concepts of decomposition and composition. The meaning of a unified approach is defined in a sense that, in order to solve a design problem to meet a certain requirement such as security or complexity or performance, an integrated thinking process utilizing both decomposability and composability is employed. This work is done at an architectural and design level. The main idea of our study is rooted from the study of the structural properties of finite state machines. We introduce the notion of (n, m)-design in some detail and illustrate the main idea using an example. Finally, we provide a list of potential applications.

The evolution of processor architectures from multi-core to many-core requires programmers to use concurrency to achieve performance. Unfortunately, shared memory parallel programs are difficult to implement correctly, and so is detecting concurrency bugs (e.g., data races, deadlocks, order violations, atomicity violations). In practice, the most common concurrency bugs are a) data races that arise due to unguarded or improperly guarded memory updates and b) deadlocks that arise due to circular dependencies among locks. While data races can be ameliorated by appropriate synchronization (a challenging problem in itself), deadlocks require fairly complex deadlock avoidance techniques, which may fail when the order of lock acquisitions is not known a priori. Furthermore, due to the potential for deadlocks, programmers cannot arbitrarily compose lock based codes without knowing the internal locking structure. Hence, composability is limited by deadlocks. The goal of this research is to achieve composability of lock based codes.

In this paper we examine composability properties for the fundamental task of key exchange. Roughly speaking, we show that key exchange protocols secure in the prevalent model of Bellare and Rogaway can be composed with arbitrary protocols that require symmetrically distributed keys. This composition theorem holds if the key exchange protocol satisfies an additional technical requirement that our analysis brings to light: it should be possible to determine which sessions derive equal keys given only the publicly available information. What distinguishes our results from virtually all existing work is that we do not rely, neither directly nor indirectly, on the simulation paradigm. Instead, our security notions and composition theorems exclusively use a game-based formalism.We thus avoid several undesirable consequences of simulation-based security notions and support applicability to a broader class of protocols. In particular, we offer an abstract formalization of game-based security that should be of independent interest in other investigations using game-based formalisms.

International audience; Computational soundness results show that under certain conditions it is possible to conclude computational security whenever symbolic security holds. Unfortunately, each soundness result is usually established for some set of cryptographic primitives and extending the result to encompass new primitives typically requires redoing most of the work. In this paper we suggest a way of getting around this problem. We propose a notion of computational soundness that we term deduction soundness. As for other soundness notions, our definition captures the idea that a computational adversary does not have any more power than a symbolic adversary. However, a key aspect of deduction soundness is that it considers, intrinsically, the use of the primitives in the presence of functions specified by the adversary. As a consequence, the resulting notion is amenable to modular extensions. We prove that a deduction sound implementation of some arbitrary primitives can be extended to include asymmetric encryption and public data-structures (e.g. pairings or list), without repeating the original proof effort. Furthermore, our notion of soundness concerns cryptographic primitives in a way that is independent of any protocol specification language. Nonetheless, we show that deduction soundness leads to computational soundness for languages (or protocols) that satisfy a so called commutation property.

Embedded systems must interact with their real-time environment in a timely and dependable fashion. Most embedded-systems architectures and design processes consider “non-functional” properties such as time, energy, and reliability as an afterthought, when functional correctness has (hopefully) been achieved. As a result, embedded systems are often fragile in their real-time behaviour, and take longer to design and test than planned. Several techniques have been proposed to make real-time embedded systems more robust, and to ease the process of designing embedded systems: 1. Precision-timed and time-triggered architectures, to make time a first-class citizen of system design. 2. Deterministic architectures for repeatable timing behaviour. 3. Composability, which guarantees that the (non)-functional behaviour of components is unchanged on integration in a larger system. The tutorial presents the state of the art and major approaches to time-predictability and composability, such as BIP, TTA, PRET, PTIDES, Giotto, and CompSOC.

The design of next-generation systems running streaming applications is becoming extremely challenging as these systems are executing many real-time applications concurrently. To address this design challenge, predictable multi-processor systems-on-chip platforms and accompanying model-based design approaches are being developed. This tutorial presents an overview of future platforms and design approaches needed to design next-generation embedded systems for real-time streaming applications. During the hands-on session the participants apply this theory to a practical example.

The complexity of Networked Embedded Systems (NES) has been growing steeply, due to increases both in size and functionality, and is becoming a major development concern. This situation is pushing for paradigm changes in NES design methodologies towards higher composability and flexibility. Component-oriented design technologies, in particular supported by server-based scheduling, seem to be good candidates to provide the needed properties. As a response we developed a multi-level hierarchical server-based architecture for Ethernet switches that provides composability and supports online adaptation and reconfiguration. This paper extends our work, presenting the associated response-time based schedulability analysis, necessary for the admission control procedure. Additionally, we have derived the temporal complexity of the analysis, which is shown to be O(n2), where n is the number of higher priority components associated with a given server. Finally, we present a proof-of-concept implementation and a set of experimental results that validates the analysis.

Current policy languages come with a monolithic syntax and support only a limited set of security formalisms. Thus, contemporary policies can only inadequately prescribe the correct behavior of a distributed business application w.r.t. different views, such as usage control, safety properties, or governance. To support composing policies that involve multiple views, we propose to include well-established composability mechanisms into policy languages. In this paper, we propose an extensible security DSL that composes multiple mechanisms---namely inheritance, scoping, aspects, and different paradigms---into one composite policy language.

1. THE HEALTHOS SYSTEM Recently, an increasing number of pervasive healthcare applications have been developed as a way to overcome the shortcomings of the traditional clinical infrastructure. However, the nature of these applications, both closed and vertically-integrated, hinders integration with the existing infrastructure, increases the development cost, and fails to provide a unified management interface. In response to these challenges, we propose HealthOS, a platform designed to develop pervasive healthcare applications. Figure 1 illustrates the target environment for HealthOS. As the figure suggests, HealthOS users can carry multiple healthcare-related devices in their living environments, each using their proprietary communication protocols and data formats. HealthOS collects, encrypts, and stores the data on either a local machine or in a secure cloud service. Upon request, HealthOS can translate the data into requested formats that different healthcare applications may require. From the perspective of an application developer, the attractiveness of the HealthOS platform lies in the need to implement only the analysis and representation logic of the application. We also envision the use of a HealthStore (similar to the Apple AppStore), in which pre-developed applications can be shared and reused. The various applications are handled using the unified management console in HealthOS. Furthermore, HealthOS can be adapted to mobile platforms. Achieving our vision of HealthOS, requires implementing several modules for each device. First, a module is necessary to communicate with each device and translate the custom data that it produces. We call this module a HealthOS driver. Secondly, the formats used to present the data to different stakeholders (e.g., family members, healthcare professionals, etc.) may differ. Thus, HealthOS uses a translator module used for converting a device’s proprietary data format to match well-defined, standardized medical data presentation formats used by major electronic medical record (EMR) systems [2, 6]. Both drivers and translators follow a component-based design in the sense that they provide and require well-defined interfaces for inter-module interaction and reuse. Given that data can successfully be collected and interpreted using HealthOS, application developers can focus solely on properly

Although asynchronous communication is an important feature of many concurrent systems, building composable abstractions that leverage asynchrony is challenging. This is because an asynchronous operation necessarily involves two distinct threads of control -- the thread that initiates the operation, and the thread that discharges it. Existing attempts to marry composability with asynchrony either entail sacrificing performance (by limiting the degree of asynchrony permitted), or modularity (by forcing natural abstraction boundaries to be broken). In this paper, we present the design and rationale for asynchronous events , an abstraction that enables composable construction of complex asynchronous protocols without sacrificing the benefits of abstraction or performance. Asynchronous events are realized in the context of Concurrent ML's first-class event abstraction. We discuss the definition of a number of useful asynchronous abstractions that can be built on top of asynchronous events (e.g., composable callbacks) and provide a detailed case study of how asynchronous events can be used to substantially improve the modularity and performance of an I/O-intensive highly concurrent server application.