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A new method for reducing power and area of standard cell ASICs is described. The method is based on deliberately introducing clock skew without the use of extra buffers in the clock network. This is done by having some flipflops, called sources, generate clock signals for other flipflops, called targets. The method involves two key features: (1) the design of new differential flipflop, referred to as KVFF, that is functionally identical to a master-slave edge-triggered D flipflop, but in addition, produces an completion signal that is a skewed version of its input clock, which is used to clock other flipflops; and (2) an efficient algorithm that identifies the sources and targets involved in the new clocking scheme, with the objective of reducing area and power. These are reduced because deliberate skew introduces extra slack on the logic cones that feed the target flipflops, which is exploited by synthesis tools to reduce area and power. In addition, the overhead of conventional methods of introducing skew, e.g. buffers, is eliminated. Using commercial tools, significant improvements in power and area are shown on placed and routed netlists of several circuits.

In this paper, we present a variable node clock network and a power model to estimate leakage power in CMOS processor. Design of clock delivery network is a constrained optimization problem. A variable rate clock network is provided to reduce unwanted switching as well as to limit active clock routing network. We propose two power models to estimate processor performance under variable rate clock signal. Overall this optimization method provides improved in power and performance in current CMOS processor.

Approximate computing is an emerging paradigm to improve the efficiency of computing systems by leveraging the intrinsic resilience of applications to their computations being executed in an approximate manner. Prior efforts on approximate hardware design have largely focused on circuit-level techniques. We propose a new approach, clock overgating, for the design of approximate circuits at the Register Transfer Level (RTL). The key idea is to gate the clock signal to selected Flip-Flops (FFs) in the circuit, even during execution cycles in which the circuit functionality is sensitive to their state. This saves power in the clock tree, the FF itself and in its downstream logic, while a quality loss ensues if the erroneous FF state propagates to the circuit output. We develop a systematic methodology to identify an energy-efficient overgating configuration for any given circuit and quality constraint. Towards this end, we develop 3 key strategies — significance-based overgating, grouping FFs into overgating islands, and utilizing internal signals of the circuit as triggers for overgating — that efficiently prune the large space of possible overgating configurations. We evaluate clock overgating by designing approximate versions of 6 machine learning accelerators, and demonstrate energy benefits of 1.36x on average (and upto 1.80x) for negligible (

We present the clock architecture of the Stratix?10 FPGA, which uses a routable clock network rather than the fixed clock networks of previous generations. We describe the flexibility provided by this routable clock network and how arbitrarily sized clock trees can be synthesized and placed anywhere on the FPGA. We show how this capability to generate customized clock trees can provide better performance through reduced clock loss while maintaining the ability to handle the large number of clock domains that modern systems require. We experimentally demonstrate how a routable clock tree reduces the clock loss of the user design implementation by up to 6% of clock insertion delay.

The clock networks of modern circuits must be able to operate in multiple corners and multiple modes (MCMM). Earlier studies on clock network synthesis for MCMM designs focus on the legalization of an initial clock network that has timing violations in different corners or modes. We propose a mode reconfigurable clock tree (MRCT) that is based on a correct-by-construction approach. An MRCT consists of multiple clock trees. Depending on the active mode, the MRCT is reconfigured such that one of the clock trees is activated to deliver the clock signal. To limit the overhead, the bottom part of the network (closer to the clock sinks) is shared among all of the clock trees, and only the top part of the network (closer to the clock source) is mode reconfigurable. The reconfiguration is realized using or-gates and a single one-input-multiple-output demultiplexer. The MRCT is constructed in a bottom-up fashion by iteratively merging subtrees to form larger subtrees. When two sub-trees cannot be merged because of mode-incompatible constraints, an or-gate is inserted to separate the incompatible modes. Corner-incompatible constraints are resolved by reducing safety margins of appropriate skew constraints. The experimental results show that for a set of synthesized MCMM circuits with 715 to 13, 216 sequential elements, the proposed approach can achieve high yield.

With aggressive technology scaling in nanometer regime, a significant fraction of dynamic power is consumed in the clock network due to its high switching activity. Clock networks are typically synthesized and routed to optimize for zero clock skew. However, clock skew optimization is often accompanied with routing overhead which increases the clock net capacitance thereby consuming more power. In this paper, we propose a skew bounded buffer tree resynthesis algorithm to optimize clock net capacitance after the clock network has been synthesized and routed. Our algorithm restricts the skew of the designs within a specified margin from its original skew, and does not introduce any additional Design Rule Check (DRC) violation. Experimental results on industrial designs, with clock networks synthesized and routed by an industrial tool, have demonstrated that our approach can achieve an average reduction of 5.6% and 3.5% in clock net capacitance and clock dynamic power respectively with a marginal overhead in the clock skew.

Clock skew scheduling is a common and well known technique to improve the performance of sequential circuits by exploiting the mismatches in the data path delays. Existing clock skew scheduling techniques, however, cannot effectively consider heavily gated clock networks where a local clock tree exists between clock gating cells and registers. A methodology is proposed in this paper to efficiently achieve clock skew scheduling in circuits with gated clock networks. The methodology is implemented via both linear programming and constraint graph based approaches, and evaluated using the largest ISCAS'89 benchmark circuits with clock gating. The results demonstrate up to approximately 21% reduction in clock period while maintaining the power savings achieved by clock gating. A conventional design flow is used for the experiments, demonstrating the applicability of the proposed algorithms to automation.

This paper studies the impact of clock mismatches in spatially distributed real-time control systems. We consider a configuration in which sensor measurements are collected by one processor that transmits the measurements to another control/actuation processor through a network, but the two processors do not have a common clock. Due to the clock mismatch, there will be an offset between the actual time at which a measurement is taken and the time reported by the sensor. Our goal is to discover fundamental limitations to the ability to stabilize the control loop arising from the clocks mismatch. We consider time-varying bounded offsets and derive limitations on the offset bound for the stability of the feedback system. For the case of a scalar linear process, there exists a critical limitation, which depends on the level of instability of the plant and the nominal sampling period. In contrast, for the vector linear processes, if the process dynamics has at least two distinct real eigenvalues, then there is no fundamental limitation on the offset bound.

In this paper, we minimize 3D clock power using shutdown gates to selectively turn off unnecessary clock activities. In 3D-IC, shutdown signals require large-sized Through-Silicon-Vias(TSVs), so we propose a simulated annealing(SA) based algorithm along with a force-directed TSV placer to decide the selection of shutdown gates and the locations of TSVs under layout whitespace constraint. Furthermore, we recognize optimal power saving is achieved when the clock tree itself is designed simultaneously with the shutdown network. Experimental results show that our heuristic decreases the total clock power by more than 20% with less than 1.5% wirelength overhead while ensuring zero clock skew.

Clock grid is a mainstream clock network methodology for high performance microprocessor and SOC designs. Clock skew, power usage and robustness to PVT (power, voltage, temperature) are all important metrics for a high quality clock grid design. Tree-driven-grid clock network is a typical clock grid clock network. It includes a clock source, a buffered tree, leaf buffers, a mesh clock grid, local clock buffers, and latches as shown in Fig. 1. For such network, one big challenge is how to connect the leaf level buffers of the global tree to the grid with nonuniform loads under tight slew and skew constraints. The choice of tapping points that connect the leaf buffers to the clock grid are critical to the quality of the clock designs. Good tapping points can minimize the clock skew and reduce power. In this paper, we proposed a new algorithm to select the tapping points to build the global tree as regular and symmetric as possible. From our experimental results, the proposed algorithm can efficiently reduce global clock skew, rising slew, maximum overshoot, reduce power, and avoid local skew violation.

The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock gating cells, multiplexers and dividers) in order to achieve aggressive clock gating and required performance across a wide range of operating modes and conditions. As a result, clock tree structures have become very complex and difficult to optimize with automatic clock tree synthesis (CTS) tools. In advanced process nodes, CTS becomes even more challenging due to on-chip variation (OCV) effects. In this paper, we present a new CTS methodology that optimizes clock logic cell placements and buffer insertions in the top level of a clock tree. We formulate the top-level clock tree optimization problem as a linear program that minimizes a weighted sum of timing slacks, clock uncertainty and wirelength. Experimental results in a commercial 28nm FDSOI technology show that our method can improve post-CTS worst negative slack across all modes/corners by up to 320ps compared to a leading commercial provider's CTS flow.

Clock network is a dedicated network for distributing multiple clock signals to every logic modules in a system. Be significantly different from ASIC where the clock tree is custom built by users, clock network in FPGA is usually fixed after chip fabrication and cannot be changed for different user circuits. This paper is committed to design and implement FPGA clock network with low latency and skew. We first propose a novel clock network for FPG, which is a backbone-branches topology and can be easily integrated to the tiled FPGA with reasonable area. There are one clock backbone and several primary clock branches in the network. When the chip scales up, this clock network can be extended easily. Afterwards, series of strategies such as hybrid multiplexer, bypassing, looping back and Programmable Delay Adjustment Unit (DAU) are employed to optimize latency and skew. Moreover, the prominent couple capacitance and crosstalk effect of clock routing in nanometer are also given consideration in physical implementation. This clock network is applied to own-designed FPGA with 65nm technology. Post-layout simulation results indicate that our clock network with normal loads can uphold 600MHz clock with the maximum clock latency and skew being typically 2.22ns and 40ps respectively, 1.79ns and 39ps in the fast case, achieving up to 78.2% improvement for skew as well as 47.5% for latency, compared to a commercial 65nm FPGA device.

Treating clock drift to avoid message collision and loss is a major challenge when the Time Division Multiple Access (TDMA) protocol is used to schedule communication over a shared medium in networks. We consider clock drift in synchronized networks with tree topology and limited energy, where the root provides the reference clock. We provide a formal approach for analyzing the effect of the slot assignment on the maximal clock drift, given an upper bound on the drift rates of the clocks. We give exact topological characterizations of the slot assignments with largest and least existing clock drift and provide least upper bounds on the clock drift in both cases. We apply our results to derive an optimal, i.e. minimal, safe guard time which effectively avoids message collision or loss due to clock drift.

Meeting clock skew constraint is one of the most important tasks in the synthesis of clock trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals varies dynamically during execution. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be adjusted dynamically can solve the clock skew variation problem effectively. However, inserting ADBs requires non-negligible area and control overhead. Thus, all previous works have invariably aimed at minimizing the number of ADBs to be inserted, particularly under the environment of multiple power modes in which the operating voltage applied to some modules varies as the power mode changes. In this work, unlike the previous works which have solved the ADB minimization problem heuristically or locally optimally, we propose an elegant and easily adoptable solution to overcome the limitation of the previous works. Precisely, we propose an O(n log n) time (bottom-up traversal) algorithm that (1) optimally solves the problem of minimizing the number of ADBs to be inserted with continuous delay of ADBs and (2) enables solving the ADB insertion problem with discrete delay of ADBs to be greatly simple and predictable. In addition, we propose (3) a systematic solution to an important extension to the problem of buffer sizing combined with the ADB insertion to further reduce the ADBs to be used.

This paper introduces a novel multi-voltage domain clock mesh design methodology that is effective under multiple process corners. In multi-voltage designs, a single clock mesh that spans multiple voltage domains is infeasible due to the incompatibility of voltage levels of the clock drivers on the electrically-shorted mesh-each voltage domain requires a separate mesh. The skew among these isolated meshes need to be matched and a novel premesh tree synthesis is required to tolerate the impact of PVT variations exacerbated due to the separation of clock meshes for multiple voltage levels. The experiments performed with the largest three ISCAS'89 benchmark circuits operating at 500 MHz, 90 nm technology and 3 process corners show that: 1) The multi-voltage domain clock mesh can achieve up to 42% lower power on average with 39.04 ps skew, as low as ≈1.95% of the clock period, on average over a typical single voltage domain clock mesh, and 2) multi-corner optimized multi-voltage domain clock mesh can decrease the global skew of all corners by 190.42 ps on average over a multi-voltage domain clock mesh optimized for a single corner with a 15% degradation in power consumption necessary for variation-tolerance.

A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in the design. This is the first work known in literature that encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. Experimental results show that with gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The proposed method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

Clock distribution networks consume a significant portion of on-chip power. Traditional buffered clock distribution power is limited by frequency, capacitance, and activity rates. Resonant clock distributions can reduce this power by "recycling" energy on-chip and reducing the overall clock power. This tutorial introduces recent techniques for distributed-LC, traveling wave, and standing wave resonant clock distributions. In particular, the tutorial discusses the recent developments and open research problems. The tutorial covers both circuits, computer-aided design algorithms and methodologies for resonant clocking.

Multi-clock domain circuits with Clock Domain Crossing (CDC) interfaces are emerging as an alternative to circuits with a global clock. CDC interfaces are susceptible to metastability, hence their design is very challenging. This paper presents a hybrid FIFO-asynchronous method for constructing robust CDC interfaces. The proposed design can handle arbitrary clock frequency ratios between the sender and receiver with random phase shifts. The proposed design avoids latency due to synchronizers with the asynchronous protocol modifications. Circuit simulation results confirm the operation and robustness of the design at maximum workloads, and arbitrary frequency ratios, over a temperature range of -50 to 50 degrees Celsius. The interface offers a maximum throughput of 606 million transfers per second without pausing the clock.

Link based non-tree clock network is an effective and economic way to reduce clock skew caused by variations. However, it is still an open topic where links should be inserted in order to achieve largest skew reduction with smaller extra resources. We propose a new method using linear program to solve this problem in this paper. In our approach, clock skew in a non-tree clock network is computed using the delay model in [13] and the information is used to select the node pairs for link insertion. Tradeoff between crosslink length and skew reduction effect is explored. Based on the analysis, we propose a new algorithm to insert crosslinks into a clock network. We compare our work with the method in [1] and a recent work [4] which inserts links between internal nodes of a tree. Experiments show that our method can reduce skew under variations effectively.

We propose cross clock-domain time-division-multiplexing (TDM) Virtual Circuit (VC), in short, VC, to provide delay and bandwidth guaranteed communication for NoCs with multiple clock domains. The cross-domain VC extends the synchronous VC in a single clock domain to multiple clock domains. The synchronous VCs reserve cyclic time slots at each node from source to destination for a traffic flow to use shared links without contention based on the assumption that all nodes share the same notion of time. However, when VCs pass multiple clock domains with different phases and frequencies, the assumption of global synchrony is not valid any more and consequently they cannot function correctly. This paper addresses this problem based on a typical FIFO clock domain interface. We give the conditions and a realization scheme to ensure correct packet delivery with QoS for VCs crossing multiple clock domains. We apply network calculus to analyze and derive the bounds of the packet delay and the FIFO size.

The International Symposium on Physical Design (ISPD) 2010 contest presents the challenge of synthesizing clock distribution networks that are tolerant to severe power-supply and wire-width variations. In particular, a robust clock network should satisfy the local clock skew (LCS) constraint, i.e., the clock skew between any pair of sequential elements that are closer than a user-specified distance is below a user-specified limit, even in the presence of variations. In this paper, we identify a few factors that help in tolerating these variations in clock trees. Our proposed clock tree router uses a two-stage flow to construct low-power clock trees for which the LCS constraints are met. Our clock tree router has been tested on ISPD'10 contest benchmark circuits. Extensive Monte-Carlo simulations showed that low power clock tree solutions could effectively handle variations, even when we imposed more stringent conditions in the experimental setup.

Clock distribution in VLSI designs is of crucial importance and it is also a major source of power dissipation of a system. For today's high performance microprocessors, clock signals are usually distributed by a global clock grid covering the whole chip, followed by post-grid routing that connects clock loads to the clock grid. Early study [2] shows that about 18.1% of the total clock capacitance dissipation was due to this post-grid clock routing (i.e., lower mesh wires plus clock twig wires). This post-grid clock routing problem is thus an important one but not many previous works have addressed it. In this paper, we try to solve this problem of connecting clock ports to the clock grid through reserved tracks on multiple metal layers, with delay and slew constraints. Note that a set of routing tracks are reserved for this grid-to-ports clock wires in practice because of the conventional modular design style of high-performance microprocessors. We propose a new expansion algorithm based on the heap data structure to solve the problem effectively. Experimental results on industrial test cases show that our algorithm can improve over the latest work on this problem [1] significantly by reducing the capacitance by 24.6% and the wire length by 23.6%. We also validate our results using hspice simulation. Finally, our approach is very efficient and for larger test cases with about 2000 ports, the runtime is in seconds.

Clock power is the major contributor to dynamic power for modern IC design. A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering such cells and forming a multi-bit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, even can save the clock network power and facilitate the skew control. Hence, in this paper, we focus on multi-bit flip-flop clustering at post-placement to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-size sequences as our representation. Without enumerating all compatible combinations, we extract only partial sequences that are necessary to cluster flip-flops at a time, thus leading to an efficient clustering scheme. Moreover, our coordinate transformation brings fast operations to execute our algorithm. Experimental results show the superior efficiency and effectiveness of our algorithm.

This paper discusses a novel clock gating cell (CGC) optimized for low-power and low-voltage operation. First, the limitations of the conventional CGC topology are analyzed and several improvements are proposed. Next, the new CGC topology is introduced and compared to the conventional one in terms of dynamic clock power, leakage, area, timing, and low-voltage operation. Finally, the paper discusses the silicon measurements taken to verify the correct functionality of the new circuit in a 45-nm technology optimized for low standby power.

Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured. There are two key components in the skew synchronization scheme: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous researchers have emphasized on ADB placement issues. In this paper, we show that the connection between FFs and PDs can also greatly influence the final clock skew due to the insertion of the PDs. We first analyze the influence of PD connection structures. Then we propose an algorithm to generate a PD connection structure which achieves the minimum influence to the clock skew. Our experimental results are very encouraging.

Interconnect has come to be a dominant factor in on-chip signal propagation, skew and jitter. As frequencies increase, more accurate modeling of the wires is necessary in order to properly estimate clock propagation. However, most wire models for clock network synthesis are based on Elmore delay, a simple first-order RC model. In this work, we analyze the discrepancies between RC, RLC and transmission line models on both skew and jitter of clock trees and grids. From our experiments, the difference in skew can be as great as 45% of the clock period for transmission lines and 7.5% for the RLC model. We argue that a deeper investigation into accurately modeling long interconnect should become a higher priority in clock network synthesis

We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular standard cell approach that compensates intra-die temperature and process variances. Our clock distribution provides control over regional clock skew, permits use in beneficial skew applications and facilitates silicon-debug. By adding routing to the serial clock network, we permit post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability to the network.

Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, variability in clock networks is either handled early in the design flow by assigning margins to clock network delays, or at a later stage through post-processing steps that only focus on achieving minimal skew, without regard to functional block variability. In this work, we present a technique that alters clock network lines so that the circuit meets its timing constraints at all process corners. This is done near the end of the design flow while considering delay variability in both the clock network and the functional blocks. Our method operates at the physical level and provides designers with the required changes in clock network line widths and/or lengths. This can be formulated as a Linear Programming (LP) problem, and thus can be solved efficiently. Empirical results for a set of ISCAS-89 benchmark circuits show that our approach can considerably reduce the effect of process variations on circuit performance.

Power and variation are the biggest concerns of physical design today. Clock distribution network is at the center of both the power and variation concerns. Clock distribution networks consume a lion's share of the total IC power consumption for two reasons. First, the clock distribution network requires many large buffers to deliver crisp clock signals across a large area of the IC. Second, the clock distribution network uses many small buffers to balance the clock skews. Clock distribution networks are also most susceptible to variation for two reasons. First, both the latency and length of a clock path are usually much longer than those of typical timing paths. Second, variations to clock path delays may have a 2X impact to the timing of a timing path. Let's consider a timing path between a launching and a capturing flop and suppose that the clock path to the launching flop is sped up by 100ps and the clock path to the capturing flop is slowed down by 100ps due to variation. The impact to the hold constraint of the timing path would be 200ps. Our customers have seen chip failures due to hold violations caused by variation in this manner. Therefore, for 45nm technology nodes and beyond, we believe that a power-efficient and variation-tolerant clock distribution network is a necessary condition for a competitive IC product. In this talk we discuss the industrial clock design problems, designers' strategies for resolving the problems and the capabilities of commercial tools that we must provide to support the designers.

Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx Virtex-5 FPGA are presented. The approaches are unique in that they leverage specific architectural aspects of Virtex-5 to achieve reductions in dynamic power consumed by the clock network. The first approach comprises a placement-based technique to reduce interconnect resource usage on the clock network, thereby reducing capacitance and power (up to 12%). The second approach borrows the "clock gating" notion from the ASIC domain and applies it to FPGAs. Clock enable signals on flip-flops are selectively migrated to use the dedicated clock enable available on the FPGA's built-in clock network, leading to reduced toggling on the clock interconnect and lower power (up to 28%). Power reductions are achieved without any performance penalty, on average.

Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the control of clock skew becomes difficult. Based on that observation, in this paper, we present a novel clock tree design style, called type-matching clock tree, to ensure that the logic gates at the same level are in the same type. We prove that any clock control logic can always be transformed to our type-matching clock tree. Then, based on the idea of type-matching clock tree, we propose a zero skew gated clock tree synthesis algorithm. Compared with the industry- strength gated clock tree synthesis, experimental data show that our approach can significantly reduce the clock skew in every process corner with a small penalty on the clock tree area and the clock tree power consumption.

Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions under which the transition of a register may be safely blocked can either be explicitly specified by the designer or detected automatically. We introduce a new method for automatically synthesizing these conditions in a way that minimizes netlist perturbation and is both timing- and physical-aware. Our automatic method is also scalable, utilizing simulation and satisfiability tests and necessitating no symbolic representation. On a set of benchmarks, our technique successfully reduces the dynamic clock power by 14.5% on average. Furthermore, we demonstrate how to apply a straightforward logic simplification to utilize resulting don't cares and reduce the logic by 7.0% on average.

Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock gating in order to extract stronger gating conditions for blocks that are poorly gated or not gated at all. A second contribution of our paper is a robust and scalable approach to extract stability conditions for clock gating. Finally, we present a uniform treatment of unobservability and stability as dual approaches for propagating gating conditions forward and backward. Experimental results demonstrate significant power reduction (in the range of 14% -- 55% of the clock power) on Intel micro-processor designs.

Clock distribution networks are extremely critical from a performance and power standpoint. They account for about 20-30% of the total power dissipated in current generation microprocessors. Many three-dimensional (3D) schemes propose to reduce interconnect length to improve performance and decrease power consumption. In this paper we propose a clock distribution network for a 3D multilayer core microprocessor. The 3D microprocessor floor plan has a single core folded onto multiple layers. A separate layer for the clock distribution network is proposed in the 3D microprocessor. This arrangement of a 3D chip stack reduces (a) power lost in long interconnects at block level and (b) in the clock distribution. Simulation results indicate a 15-20% power saving for this clock distribution scheme as compared to a 2D structure. A methodology for turning off the global clock grid along with the logic for an entire layer in a 3D stack is also proposed. Simulation results indicate an additional 8-10% savings in power with minimal impact on the critical parameters of the clock grid.

Clock gating is one of the most effective techniques to reduce clock network power dissipation. Although it has already been studied considerably, most of the previous works are restricted to either logic level or clock routing stage. Due to the restriction, clock gating often meets the trouble of wirelength overhead and frequent control signal switching, both of which degrade its effectiveness. Furthermore, previous design flows which insert gate logics after placement introduce a lot of overlaps, especially when there are lots of gate logics inserted. In this work, we propose a new design flow for low power gated clock network construction, in order to minimize the clock wirelength and the activity of control signals, and to eliminate the overlaps incurred by the gate logics. Our method begins with a coarse placement followed by soft register clustering. Then, we perform clock tree topology construction and zero skew clock routing to further reduce the power and the clock skew. Last, the gated clock network is fed back to the placer for incremental placement. Experimental results on ISCAS89 benchmarks demonstrate that our method outperforms previous algorithm of activity aware register placement in clock wirelength and clock power reduction with signal nets wirelength and signal nets power increase within 5% and 3%, respectively

In this paper we argue that achieving symmetric errors is the key to an improved understanding of clock synchronization. We present a clock synchronization algorithm with drift compensation that implements this symmetric error paradigm. The performance of the algorithm is evaluated by measurements in an indoor testbed using the TinyNode hardware platform. We show that the remaining error is symmetric and in the range of the clock granularity.

We present a low-cost on-line system for clock skew management in integrated circuits. Our built-in clock skew system (BICSS) uses a centralized approach to identify, quantify and correct skew using a two-step method. The technique assesses the time-off-light between the central debug circuitry and each region, or tap under test to account for the measurement error due to differences in path length common in existing techniques. The system can be used to detect skew above a user-adjustable margin using a variable tolerance phase detector. The result is a solution which provides silicon debug and repair capability of on-chip clock skews with a very small area overhead.

The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signaling in the gigahertz range (we are able to achieve clock rates of 8 GHz and above). The clock is transported as an oscillatory wave on a pair of conductors. An oscillatory standing wave is formed across a transmission line loop, which is connected beginning-to-end through a Mobius configuration. A single cross coupled inverter pair is required to maintain oscillation across the ring. The design is aimed to achieve low skew, low power and extreme high frequency global clock situations. The energy recycling nature of a standing wave along a transmission line allows us to keep very high frequencies oscillations along a conductor with almost no power consumption at all. A special wide input range driver was designed to convert the differential signals on the coplanar transmission lines into a square clock pulse for standard clock sinks. The design uses CMOS 90 nm BSim3v model cards for all simulations, with the transmission lines implemented on Metal8.

This paper discusses the technology limits placed on the clock switching energy in sequential elements. It proposes a novel pulsed latch that uses a single clocked transistor and consumes close to ten times less clock power than a conventional latch using six clocked transistors. It describes how the new circuit enables additional power savings when virtual grounds, instead of a regular clock, are locally distributed to a group of latches. Finally, the paper discusses how to further reduce the dynamic clock power consumption of the new latch without degrading its timing by feeding it a low-swing clock.

QoS-support technology in networks is based on measuring QoS metrics which reflect a magnitude of stability and performance such as delay, delay variation, available bandwidth and packet error rate and so on. The measurement of one-way delay essentially requires a guarantee of clock synchronization between end-to-end hosts. However, the hosts in networks have a relative or absolute difference in clock time by reason of clock offsets, clock skews and clock adjustments. In this paper, we propose theory and method of estimating one-way delay and clock offset between end-to-end hosts using our proposed theorem, which is derived from a relationship between one-way delays, one-way delay variations and round-trip times.

This paper presents a circuit optimization technique called skewspreading. Given an edge-triggered sequential circuit, skew spreadingderives the required clock arrival times for all registers so that theskews are distributed evenly in a preselected time window without changing the operating frequency of the circuit. Skew spreading is ideal for peak current reduction, since it distributes clock activities and the ensuing signal activities widely in time. We have developed a skew spreading algorithm and applied it to a suite of benchmark circuits. Simulation results demonstrate that the variance of the resulting skew from the uniform distribution can be reduced to 4% on the average. In comparison to other gate-level peak current reduction techniques, our scheme achieves an average improvement of 17% with a speedup of up to 13.9 times.

In this paper, we present an approach for low--power driven synthesis based on local frequency/voltage scaling. During the scheduling phase of the High--Level Synthesis (HLS) the design is partitioned into different frequency/voltage islands. Operators within these islands, are encapsulated by wrappers to ensure correct dataflow between the islands. A wrapper consists of a clock generator and input- and output ports. The local clocks are calculated by dividing the global clock signal. With the developed wrappers we are able to automatically integrate local frequency/voltage scaling for our target architecture by our HLS tool. As an example we implement the inverse discrete cosine transformation (IDCT).

The evolution of VLSI chips towards larger die size, smaller feature size and faster clock speed makes the clock distribution an increasingly important issue. In this paper, we propose a new clock distribution network (CDN), namely Variant X-Tree, based on the idea of X-Architecture proposed recently for efficient wiring within VLSI chips. The Variant X-Tree CDN keeps the nice properties of equal-clock-path and symmetric structure of the typical H-tree CDN, but results in both a lower maximal clock delay and a lower clock skew than its H-tree counterpart, as verified by an extensive simulation study that incorporates simultaneously the effects of process variations and on-chip inductance.

A novel differential pulse-width control loop circuit based on high speed frequency-to-voltage converters is proposed. To demonstrate its functionality, a circuit has been designed and simulated in 0.18mm CMOS technology. Results show that the proposed circuit can correct a clock signal's duty cycle even for frequencies as high as 5 GHz. This design can be used to correct clock signal distortion due to process variations in high speed applications such as half-rate clock and data recovery systems.

We study the problem of providing a sensor node with an accurate estimate of the current time, from a novel prospective which is complementary to the well--studied clock synchronization problem. More precisely, we analyze the case in which a sensor node is temporarily unable to run a clock synchronization protocol due to low--energy, or intermittent connectivity, or process failures, but still requires an accurate estimate of the time. We propose and analyze two efficient clock reading methods, one deterministic and the other probabilistic, which are designed to work in synergy with clock synchronization protocols to provide a better time estimate. Our deterministic method achieves a better accuracy by exploiting the sign of the global deviation of the hardware clock from the reference time, and can be applied to reduce the frequency of the periodic clock adjustments by a factor 2, while maintaining the same time uncertainty. The second method based on time series forecasting, is more flexible than the previous one since it is independent of the frequency at which clock synchronization occur.

This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a significant amount of redundant clock pulses. The paper presents a new theory for optimal clocking of synchronous pipelines, presents practical implementations and evaluates the clock power benefits on a multiply/add-accumulate unit design. Transistor level simulations show that dynamic clock power dissipation can be reduced by 40-60% at pipeline utilization factors between 20-60%, on top of traditional stage-level clock gating, without affecting pipeline latency or throughput.

The use of interconnected rings approach, as globally asynchronous, locally synchronous clock distribution network, offers good performance regarding scalability, low clock-skew and high-speed clocking. Moreover, they show linear metal-cost growth and the power consumption is directly proportional to number of interconnected rings. In this paper, the performance of interconnected rings, working as clock distribution networks, is analyzed and verified by experimental measurements. Typical 3.3V 0.35μm CMOS N-well AMS process parameters were used for the analysis and chip fabrication. It is shown that interconnected rings are a robust approach under parameters variations.

In this paper, a global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The key design issues involved in generating standing waves on a chip are discussed, including minimizing wire loss within an available technology. A standing-wave oscillator, a distributed oscillator that sustains ideal standing waves on lossy wires, is introduced. A clock grid architecture comprised of coupled, standing-wave oscillators and differential, low-swing clock buffers is presented. The measured results for a prototyped standing-wave clock grid operating at 10GHz and fabricated in a 0.18/spl mu/m 6M CMOS logic process are presented. A technique is proposed for on-chip skew measurements with subpicosecond precision.

An architecture that combines a Globally Asynchronous, Locally Synchronous (GALS) [1,2] design style with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimum power consumption. The proposed Globally Asynchronous, Locally Dynamic System (GALDS) requires three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently-clocked synchronous blocks [3], an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally-controlled oscillator to generate global fixed frequency clocks required by the all-digital dynamic clock generator. These circuits have been designed and simulated for all the tasks required to implement a complete GALDS infrastructure. The architecture is easily scaled due to the modular nature of these circuits and is useful for a wide range of applications.

The performance of interconnected rings and oscillators, working as clock distribution networks, is analyzed and compared among several configurations. The use of interconnected 3-inverter rings as globally asynchronous, locally synchronous clock distribution networks is proposed even for chip lengths from 4 to 24 mm. In this approach, modularity and basic cell properties are kept while the power consumption results directly proportional to the number of blocks. Typical 3.3V AMS 0.35mm CMOS N-well process parameters were used for the analysis. Regarding the current area expansion, we show that interconnected rings is a more robust approach than the interconnected oscillators.