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Water distribution networks (WDNs) are one of the largest infrastructures in society. Various methods for formulation and hydraulic analysis of water distribution networks, including numerical and non-numerical methods, have been previously proposed. Due to the complexity, the nonlinearity of the hydraulic equations of water distribution networks, and the need for multiple executions and uncertainties in parameters, solving the hydraulic model of water distribution networks has high time complexity. In this paper, a parallel computational architecture based on the concept of cellular automata is proposed to accelerate the numerical solution of the steady-state water distribution network model. Taylor series is proposed to solve hydraulic equations. The presented architecture was implemented as a parallel hardware platform on a field-programmable gate array. The performance of the proposed method was compared with EPANET software for networks with different complexities and topologies. The results show that the proposed parallel algorithm can accelerate the hydraulic analysis of regular water distribution networks up to 700 times and 250 times for small and large networks, respectively. • Proposed CA architectures to solve a system of non-linear equations on a fine-grain parallel architecture. • An efficient method to reduce computation time for hydraulic analysis of water networks. • The synthesizable hardware descriptions were generated through design automation. • Accelerate the hydraulic analysis of WDNs up to 700 times compared to EPANET, a well-known hydraulic analysis tool. [ABSTRACT FROM AUTHOR]

One of the key objectives in many fields in machine learning is to discover causal relationships among a set of variables from observational data. In linear non-Gaussian acyclic models (LiNGAM), it can be shown that the true underlying causal structure can be identified uniquely from merely observational data. The DirectLiNGAM algorithm is a well-known solution to learn the true causal structure in a high dimensional setting. DirectLiNGAM algorithm executes in a sequence of iterations and it performs a set of comparisons between pairs of variables in each iteration. Unfortunately, the runtime of this algorithm grows significantly as the number of variables increases. In this paper, we propose a parallel algorithm, called ParaLiNGAM, to learn casual structures based on DirectLiNGAM algorithm. We propose a threshold mechanism that can reduce the number of comparisons remarkably compared with the sequential solution. Moreover, in order to further reduce runtime, we employ a messaging mechanism between workers. We also present an implementation of ParaLiNGAM on GPU, considering hardware constraints. Experimental results on synthetic and real data show that our proposed solution outperforms DirectLiNGAM by a factor up to 4788X, and by a median of 2344X. • A scalable algorithm for learning causal structures in linear non-Gaussian models. • Significant speedup by selecting the necessary computations judiciously. • Speedup ratio of up to 4788 on GPUs in real-world and synthetic datasets. [ABSTRACT FROM AUTHOR]

We discuss the parallelization of algorithms for solving polynomial systems by way of triangular decomposition. The Triangularize algorithm proceeds through incremental intersections of polynomials to produce different components (points, curves, surfaces, etc.) of the solution set. Independent components imply the opportunity for concurrency. This "component-level" parallelization of triangular decompositions, our focus here, belongs to the class of dynamic irregular parallelism. Potential parallel speed-up depends only on geometrical properties of the solution set (number of components, their dimensions and degrees); these algorithms do not scale with the number of processors. To manage the irregularities of component-level parallelization we combine different concurrency patterns: map, workpile, producer-consumer, pipeline, and fork-join. We report on our implementation in the freely available BPAS library. Comprehensive experimentation with thousands of polynomial systems yields examples with up to 10.8× speed-up on a 12-core machine. [ABSTRACT FROM AUTHOR]

The L -ary n -dimensional hamming graph K L n is one of the most attractive interconnection networks for parallel processing and computing systems. Analysis of the link fault tolerance of topology structure can provide the theoretical basis for the design and optimization of the interconnection networks. The k -component edge-connectivity c λ k (G) of an interconnection network G , is the minimum number of set of faulty links, such that these malfunctions disconnect the network G with at least k connected subnetworks. It gives a more precise quantitative analysis of indicators of the robustness of a parallel distributed system in the event of faulty links. Let t = ⌊ n 2 ⌋ if L is even, and t = ⌈ n 2 ⌉ if L is odd. In this paper, we prove that the (k + 1) -component edge-connectivity of L -ary n -dimensional hamming graphs is c λ k + 1 (K L n) = (L − 1) n k − e x k (K L n) 2 for k ≤ L t , n ≥ 7 , where e x k (K L n) represents the maximum degree sum of the subgraph induced by all k processors of K L n. As the exact values of (k + 1) -component edge-connectivity of K L n oscillate greatly, an efficient O (log ⁡ N) algorithm is designed to determine the exact values of c λ k + 1 (K L n) for each k ≤ L t and N = L n. Our result improves those of Xu et al. [33] and Liu et al. [27]. • The (k + 1) -component edge-connectivity of L -ary n -dimensional hamming graphs K L n is explored. • Determine the exact value of c λ k + 1 (K L n) for each k ≤ L t and n ≥ 7 , where t = ⌊ n 2 ⌋ if L is even, and t = ⌈ n 2 ⌉ if L is odd. • An efficient O (l o g N) algorithm is designed to determine the exact value of c λ k + 1 (K L n) for each k ≤ L t and N = L n. [ABSTRACT FROM AUTHOR]

Data-intensive computing frameworks typically split job workload into fixed-size chunks, allowing them to be processed as parallel tasks on distributed machines. Ideally, when the machines are homogeneous and have identical speed, chunks of equal size would finish processing at the same time. However, such determinism in processing time cannot be guaranteed in practice. Diverging processing times can result from various sources such as system dynamics, machine heterogeneity, and variable network conditions. Such variation, together with dynamics and uncertainty during task processing, can lead to significant performance degradation at job level, due to long tails in job completion time resulted from residual chunk workload and stragglers. In this paper, we propose Forseti , a novel processing scheme that is able to reshape data chunk size on the fly with respect to heterogeneous machines and a dynamic execution environment. Forseti mitigates residual workload and stragglers to achieve significant improvement in performance. We note that Forseti is a fully online scheme and does not require any a priori knowledge of the machine configuration nor job statistics. Instead, it infers such information and adjusts data chunk sizes at runtime, making the solution robust even in environments with high volatility. In its implementation, Forseti also exploits a virtual machine reuse feature to avoid task start-up and initialization cost associated with launching new tasks. We prototype Forseti on a real-world cluster and evaluate its performance using several realistic benchmarks. The results show that Forseti outperforms a number of baselines, including default Hadoop by up to 68% and SkewTune by up to 50% in terms of average job completion time. • Forseti enables efficient data processing by reshaping data chunk sizes on the fly. • Forseti mitigates residual workload and stragglers to improve performance. • Forseti does not require any a priori knowledge. • Forseti infers tasks statistics and adjusts data chunk sizes at runtime. • Forseti exploits a virtual machine reuse feature to avoid task start-up time. [ABSTRACT FROM AUTHOR]

Deep Neural Networks (DNNs) have gained widespread popularity in different domain applications due to their dominant performance. Despite the prevalence of massively parallel multi-core processor architectures, adopting large DNN models in embedded systems remains challenging, as most embedded applications are designed with single-core processors in mind. This limits DNN adoption in embedded systems due to inefficient leveraging of model parallelization and workload partitioning. Prior solutions attempt to address these challenges using data and model parallelism. However, they lack in finding optimal DNN model partitions and distributing them efficiently to achieve improved performance. This paper proposes a DNN model parallelism framework to accelerate model training by finding the optimal number of model partitions and resource provisions. The proposed framework combines data and model parallelism techniques to optimize the parallel processing of DNNs for embedded applications. In addition, it implements the pipeline execution of the partitioned models and integrates a task controller to manage the computing resources. The experimental results for image object detection demonstrate the applicability of our proposed framework in estimating the latest execution time and reducing overall model training time by almost 44.87% compared to the baseline AlexNet convolutional neural network (CNN) model. • Parallel Computing. • Machine Learning. • DNN Model Partitioning. • Embedded Systems. • Embedded Software. [ABSTRACT FROM AUTHOR]

The k -ary n -cube Q n k serves as an indispensable interconnection network in the design of data center networks, network-on-chips, and parallel computing systems since it possesses numerous attractive properties. In these parallel architectures, the paired (or unpaired) many-to-many m -disjoint path cover (m -DPC) plays a significant role in message transmission. Nevertheless, the construction of m -DPC is severely obstructed by large-scale edge faults due to the rapid growth of the system scale. In this paper, we investigate the existence of paired 2-DPC in Q n k under the partitioned edge fault (PEF) model, which is a novel fault model for enhancing the networks' fault-tolerance related to path embedding problem. We exploit this model to evaluate the edge fault-tolerance of Q n k when a paired 2-DPC is embedded into Q n k. Compared to the other known works, our results can help Q n k to achieve large-scale edge fault-tolerance. • This research studies the existence of paired 2-disjoint path cover in k -ary n -cubes in the presence of large-scale faulty edges. • Our findings generalize the result in [50] from the theoretical perspective. • Our results provide the exponential edge fault-tolerance compared to previous similar works. [ABSTRACT FROM AUTHOR]

• Long-gauge static strain transmissibility is proposed, and its physical properties under moving loads are revealed. • Long-gauge static strain transmissibility is proved to be independent of moving loads, making it an ideal damage indicator. • Each long-gauge transmissibility is proportional to the stiffness ratio between two measured zones while remaining unaffected by other zones. • Physical properties enable decomposing damage diagnosis into independent sub-tasks on the element level, significantly reducing the training samples. • A novel element-wise parallel deep learning architecture is proposed and experimentally verified for damage diagnosis. The Transmissibility Function (TF) has gained considerable interest in structural damage detection because of its relatively high sensitivity to damage and robustness to excitation. This study proposed a distributed damage diagnosis method for beam-like structures based on a long-gauge static strain TF defined as the ratio of the Fourier transform of static strain response under moving loads from a target long-gauge sensor to that from the reference sensor. It has been discovered that each long-gauge static strain TF is independent of moving loads, making it an ideal damage indicator. It exhibits direct proportionality to the ratio of bending stiffness between the two measured zones covered by the target and reference long-gauge strain sensors while being unaffected by the stiffness of any other zones not covered by these two sensors. Moreover, the TF at zero frequency was proved to be equivalent to the ratio of static strain time history areas, relying solely on the stiffness of the covered zones. Leveraged by the physical properties of long-gauge static strain TF, an element-wise parallel deep neural network architecture was developed to decompose damage diagnosis into independent sub-tasks on the element level, utilizing a variational autoencoder (VAE) in the Bayesian inference framework for extracting features from the long-gauge strain TF and a regressor for mapping the features to elemental stiffness reduction. The divide-and-conquer strategy and element-wise parallel learning architecture allow for a significant reduction in the number of labeled training samples generated based on the updated numerical baseline model as it only requires simulated scenarios involving a single damage element. The efficiency and robustness of the proposed method were demonstrated through a numerical simply supported beam and a laboratory experiment on a two-span bridge. [ABSTRACT FROM AUTHOR]

In high performance computing environments, we observe an ongoing increase in the available number of cores. For example, the current TOP500 list reveals that nine clusters have more than 1 million cores. This development calls for re-emphasizing performance (scalability) analysis and speedup laws as suggested in the literature (e.g., Amdahl's law and Gustafson's law), with a focus on asymptotic performance. Understanding speedup and efficiency issues of algorithmic parallelism is useful for several purposes, including the optimization of system operations, temporal predictions on the execution of a program, the analysis of asymptotic properties, and the determination of speedup bounds. However, the literature is fragmented and shows a large diversity and heterogeneity of speedup models and laws. These phenomena make it challenging to obtain an overview of the models and their relationships, to identify the determinants of performance in a given algorithmic and computational context, and, finally, to determine the applicability of performance models and laws to a particular parallel computing setting. In this work, I provide a generic speedup (and thus also efficiency) model for homogeneous computing environments. My approach generalizes many prominent models suggested in the literature and allows showing that they can be considered special cases of a unifying approach. The genericity of the unifying speedup model is achieved through parameterization. Considering combinations of parameter ranges, I identify six different asymptotic speedup cases and eight different asymptotic efficiency cases. Jointly applying these speedup and efficiency cases, I derive eleven scalability cases, from which I build a scalability typology. Researchers can draw upon my suggested typology to classify their speedup model and to determine the asymptotic behavior when the number of parallel processing units increases. Also, the description of two computational experiments demonstrates the practical application of the model and the typology. In addition, my results may be used and extended in future research to address various extensions of my setting. • We develop a generic speedup and efficiency model for computational parallelization. • The unifying model generalizes many prominent models suggested in the literature. • Asymptotic analysis extends existing speedup laws. • Asymptotic analysis allows explaining sublinear, linear and superlinear speedup. • Based upon asymptotic speedup and efficiency analyses, we build a scalability typology. [ABSTRACT FROM AUTHOR]

Identifying system dynamics is an essential task for several research areas that deal with real systems intended for purposes such as control, monitoring, or fault detection. However, the nonlinear characteristics of most real systems have led to the development of techniques with high computational complexity, which can make their use unfeasible in systems with restrictions, such as embedded systems. In this case, few studies have been done on how best to map nonlinear system identification techniques to embedded system platforms that may have parallelism capabilities, such as those incorporating GPUs. This work proposes a novel software architecture for parallel model term selection and estimation for Nonlinear AutoRegressive Moving Average with eXogenous inputs (NARMAX) models, addressed to GPU-based embedded platforms. Namely, we devise a new parallel strategy to perform Forward Regression Orthogonal Least Squares (FROLS) in nonlinear black-box system identification. The architecture presented was tested in the new NVIDIA Jetson Developer Kit, which contains a 128-core Maxwell-GPU, and compared to serial versions of the algorithm run in standard Intel Core i7 CPU and ARM A57. Using a theoretical example, we defined a parallelization strategy and validated it with an electro-mechanical positioning system representing time-invariant nonlinear systems. As a result, the time spent in the proposed parallel GPU algorithm is more than 24.5x faster, and the energy-efficiency is 22x better if compared to its serial version. This represents a significant improvement in speedup and energetic demand, allowing NARMAX/FROLS models to be constructed online using low-cost and low-power embedded platforms. • Few studies focus on system identification techniques for embedded system constraints. • Mapping FROLS algorithm to GPU is not a trivial task, due to its serial structure. • A GPU-based approach enabling system identification techniques using embedded systems. • Detailed analysis of FROLS mapping to GPU aiming performance and energy consumption. • A case study showed a solution with gains in performance and energy consumption. [ABSTRACT FROM AUTHOR]

Finding a novel drug is a very long and complex procedure. Using computer simulations, it is possible to accelerate the preliminary phases by performing a virtual screening that filters a large set of drug candidates to a manageable number. This paper presents the implementations and comparative analysis of two GPU-optimized implementations of a virtual screening algorithm targeting novel GPU architectures. This work focuses on the analysis of parallel computation patterns and their mapping onto the target architecture. The first method adopts a traditional approach that spreads the computation for a single molecule across the entire GPU. The second uses a novel batched approach that exploits the parallel architecture of the GPU to evaluate more molecules in parallel. Experimental results showed a different behavior depending on the size of the database to be screened, either reaching a performance plateau sooner or having a more extended initial transient period to achieve a higher throughput (up to 5x), which is more suitable for extreme-scale virtual screening campaigns. • Analyze and compare two CUDA implementations of a real-world virtual screening application with a completely different design. • Experimental results show how a batched approach yields a much higher throughput than an approach that spreads the computation across the GPU. • To explain the performance, we performed a detailed analysis considering the algorithm, hardware characteristics, and input features. [ABSTRACT FROM AUTHOR]

Recent technological advancements have significantly expanded the potential of human action recognition through harnessing the power of 3D data. This data provides a richer understanding of actions, including depth information that enables more accurate analysis of spatial and temporal characteristics. In this context, We study the challenge of 3D human action recognition. Unlike prior methods, that rely on sampling 2D depth images, skeleton points, or point clouds, often leading to substantial memory requirements and the ability to handle only short sequences, we introduce a novel approach for 3D human action recognition, denoted as SpATr (Spiral Auto-encoder and Transformer Network), specifically designed for fixed-topology mesh sequences. The SpATr model disentangles space and time in the mesh sequences. A lightweight auto-encoder, based on spiral convolutions, is employed to extract spatial geometrical features from each 3D mesh. These convolutions are lightweight and specifically designed for fix-topology mesh data. Subsequently, a temporal transformer, based on self-attention, captures the temporal context within the feature sequence. The self-attention mechanism enables long-range dependencies capturing and parallel processing, enabling scalability for long sequences. The proposed method is evaluated on three prominent 3D human action datasets: Babel, MoVi, and BMLrub, from the Archive of Motion Capture As Surface Shapes (AMASS). Our results analysis demonstrates the competitive performance of our SpATr model in 3D human action recognition while maintaining efficient memory usage. The code and the training results are publicly available at https://github.com/h-bouzid/spatr. • Accurate 3D action prediction via spiral auto-encoder and temporal transformer. • Lightweight design for resource optimization & long sequences handeling 1000+ frames. • Evaluation on MoCap datasets: Babel, MoVi, BMLrub datasets from AMASS archive. • Competitive recognition and superior memory efficiency to state-of-the-art. [ABSTRACT FROM AUTHOR]

Unmanned Aerial Vehicles (UAVs) have exhibited its potential for efficient and non-invasive crop data acquisition in high throughput crop phenotyping. In general, for analysis of phenotypic traits, there is a need for extracting the region of interest (RoI) from images captured by UAVs. It involves the generation of orthomosaic, which is a complicated and time-intensive process. In this study, a fully automated AI-based pipeline has been proposed for the RoI segmentation from raw RGB images acquired via UAV. The proposed pipeline achieves a near real-time processing speed compared to the other baseline methods. The key feature of the pipeline is the introduction of Sub-Paths , in which the original UAV flight path is divided into several small paths which facilitates parallel processing. The image quality of the extracted RoI has been examined using blind/referenceless image spatial quality evaluator (BRISQUE) and natural image quality evaluator (NIQE). The performance of the proposed pipeline is exemplified with the Leaf Area Index (LAI) estimation on five datasets containing three different crop types and growth stages. Regression analysis has also been performed on the estimated LAI values. Average R2, RMSE, and correlation scores of the estimates are observed to be 0.68, 0.033, and 0.83, respectively. • Fully automated end-to-end AI-based pipeline avoids using orthomosaic. • Processing time for fixed field and fixed overlap is same, significantly faster than using orthomosaic. • Image quality of the extracted ROI has been analysed using BRISQUE and NIQE indices. • A plant trait has been estimated autonomously as a use case of the proposed framework. [ABSTRACT FROM AUTHOR]

• Presentation of fine tuned assignments for HPC and parallel programming courses. • All assignments tested on students in three interconnected courses. • Covering vectorization, caches, multicore CPUs, GPUs, and multi-node problems. • Introducing 5 widely used technologies (TBB, OpenMP, CUDA, OpenMPI, and Spark). Programming courses usually focus on software-engineering problems like software decomposition and code maintenance. While computer-science lessons emphasize algorithm complexity, technological problems are usually neglected although they may significantly affect the performance in terms of wall time. As the technological problems are best explained by hands-on experience, we present a set of homework assignments focused on a range of technologies from instruction-level parallelism to GPU programming to cluster computing. These assignments are a product of a decade of development and testing on live subjects – the students of three performance-related software courses at the Faculty of Mathematics and Physics of the Charles University in Prague. [ABSTRACT FROM AUTHOR]

This study advocates the utilization of a parallel neural network (PNN) architecture for the estimation of remaining useful life (RUL) of rolling element bearings. Conventional machine learning methods have often fallen short in processing machinery sensor data efficiently and accurately, given its vast nature and the temporal dynamics of component health conditions. To address this limitation, a robust PNN architecture is proposed which incorporates multiple parallel processing pathways. These pathways are equipped with diverse input neurons, capturing data from mechanical component condition sensors. The output neuron then efficiently predicts the RUL, capturing the degradation stages throughout the component's lifespan. The PNN structure provides better accuracy and computation time by efficiently handling huge amounts of data simultaneously and integrating both spatial and temporal information present. Additionally, time-transformer and recurrent neural networks (RNNs) are used to handle complex time series data. Improvement methodologies, such as positional encoding combined with a multi-headed self-attention mechanism and the convolutional long short-term memory (ConvLSTM) neural network, are employed. These methodologies adeptly handle spatiotemporal dependencies inherent in multidimensional features extracted across the time domain, frequency domain, and time–frequency domain, thereby considerably boosting the model's efficacy. Two case studies are conducted on XJTU-SY rolling element bearing dataset and FEMTO bearing dataset to validate and display the generalization capabilities of the proposed methodology, where PNN performed exceptionally in terms of accuracy and efficiency. It is concluded that with a novel implementation of variational stride temporal window strategy and utilizing the full capabilities of a PNN, the RUL of bearings can be predicted very accurately. The algorithm strategy is very robust and can be applied to other machine components as well. Subsequently, the code for the algorithm will be open-sourced. [ABSTRACT FROM AUTHOR]

Shared-memory graph processing is usually more efficient than in a cluster in terms of cost effectiveness, ease of programming and runtime. However, the limited memory capacity of a single machine and the huge sizes of graphs restrains its applicability. Hence, it is imperative to reduce memory footprint. We observe that index compression holds promise and propose CIC-PIM, a lightweight encoding with chunked index compression, to reduce the memory footprint and the runtime of graph algorithms. CIC-PIM aims for significant space saving, real random-access support and high cache efficiency by exploiting the ubiquitous power-law and sparseness features of large scale graphs. The basic idea is to divide index structures into chunks of appropriate size and compress the chunks with our lightweight fixed-length byte-aligned encoding. After CIC-PIM compression, two-fold larger graphs are processed with all data fit in memory, resulting in speedups or fast in-memory processing unattainable previously. • Spare computing power can be traded for memory space in graph processing • Memory footprint of graph processing is significantly reduced by index compression • Parallel graph processing is faster if graph is compressed with lightweight encoding. [ABSTRACT FROM AUTHOR]

Understanding memory performance in multi-core platforms is a prerequisite to perform optimizations. To this end, this paper presents analytical models based on Stochastic Reward Nets (SRNs) to model and evaluate the memory performance of Non-Uniform Memory Access (NUMA) multi-core architectures. The approach considers the details of the architecture and first proposes a monolithic SRN model that evaluates the memory performance in terms of the mean memory response time. Since the monolithic model incurs a state space explosion with an increasing number of cores and memory controllers, two approximate models are presented that are able to evaluate large-scale NUMA architectures. The SRNs are validated through measurements on two NUMA multi-core platforms, a 64-core AMD Opteron server and a 72-core Intel system. The results demonstrate the ability of the proposed models to accurately compute the mean memory response time on NUMA architectures. The results also provide valuable information that runtime systems and application designers can use to optimize execution of parallel applications on such architectures. • Understanding memory performance in NUMA architectures using stochastic reward nets. • Approximate SRN models to model large scale NUMA architectures with low complexity. • Cross-validation of the proposed SRN models on a real NUMA multi-core system. • Model-based analysis of large scale NUMA memory performance for various applications. [ABSTRACT FROM AUTHOR]

The alternating direction method of multipliers (ADMM) is a powerful operator splitting technique for solving structured convex optimization problems. Due to its relatively low per-iteration computational cost and ability to exploit sparsity in the problem data, it is particularly suitable for large-scale optimization. However, the method may still take prohibitively long to compute solutions to very large problem instances. Although ADMM is known to be parallelizable, this feature is rarely exploited in real implementations. In this paper we exploit the parallel computing architecture of a graphics processing unit (GPU) to accelerate ADMM. We build our solver on top of OSQP, a state-of-the-art implementation of ADMM for quadratic programming. Our open-source CUDA C implementation has been tested on many large-scale problems and was shown to be up to two orders of magnitude faster than the CPU implementation. • Parallel implementation of the alternating direction method of multipliers. • Preconditioned conjugate gradient method used for solving a linear system. • Solving problems with hundreds of millions nonzero entries within seconds. • Up to two orders of magnitude faster than the CPU implementation. [ABSTRACT FROM AUTHOR]

This paper presents a technique for symmetry reduction that adaptively assigns a prefix of variables in a system of constraints so that the generated prefix-assignments are pairwise nonisomorphic under the action of the symmetry group of the system. The technique is based on McKay's canonical extension framework (McKay, 1998). Among key features of the technique are (i) adaptability—the prefix sequence can be user-prescribed and truncated for compatibility with the group of symmetries; (ii) parallelizability—prefix-assignments can be processed in parallel independently of each other; (iii) versatility—the method is applicable whenever the group of symmetries can be concisely represented as the automorphism group of a vertex-colored graph; and (iv) implementability—the method can be implemented relying on a canonical labeling map for vertex-colored graphs as the only nontrivial subroutine. To demonstrate the practical applicability of our technique, we have prepared an experimental open-source implementation of the technique and carry out a set of experiments that demonstrate ability to reduce symmetry on hard instances. Furthermore, we demonstrate that the implementation effectively parallelizes to compute clusters with multiple nodes via a message-passing interface. [ABSTRACT FROM AUTHOR]

Fingerprint-based human authentication has shown great potential for civil, forensic and corporate security applications in recent years. For large-scale databases, the complexity of the identification system increases and implementing these systems on general-purpose sequential computing devices becomes challenging. Field Programmable Gate Array (FPGA) has demonstrated to be an efficient tool for the acceleration of computationally challenging applications by utilizing parallelism in the computations. In this study, an FPGA-based hardware accelerator is exploited to propose a fast and robust fingerprint identification solution that is based on a generalized minutiae neighbor based encoding and matching algorithm. The proposed FPGA implementation employs the Distributed RAM resources efficiently by using them as look-up tables for matching the encoded minutiae features. The proposed FPGA-based fingerprint matching system has the potential to match 2.75 million fingerprints per second while maintaining a low error rate. The proposed system can be deemed as an effective solution for Automated Fingerprint Identification Systems (AFIS) for large-scale applications. • A generalized minutiae-neighbor based fingerprint encoding and matching algorithm is mapped on FPGA technology. • FPGA Distributed–RAM resources are efficiently exploited as look-up tables for comparing the encoded minutiae. • The proposed FPGA based fingerprint matching system has the potential to match 2.75 million fingerprints per second while maintaining a low error rate. [ABSTRACT FROM AUTHOR]

Thus far, Multiview High-Efficiency Video Coding (MV-HEVC) can only use a central processing unit (CPU) to perform decompression on a personal computer (PC) or workstation. Because MV-HEVC is much more complex than High-Efficiency Video Coding (HEVC), decompressors need higher parallelism to decompress in real time. Therefore, this study presents a parallel method based on MV-HEVC. Inter-view complete parallelism is realized according to the dependent relationship between other MV-HEVC views, and a search range is not required to avoid the data dependence between frames. Based on the dependencies of each task in MV-HEVC, an advanced wavefront parallel processing method is proposed to achieve higher intra-frame parallelism. The parallel structure of the proposed method is compatible with that of the single-instruction multiple-data acceleration method. The results showed that the proposed method can decompress MV-HEVC with 20 threads in real time for 1088p video with three views. • We presented a parallel method based on Multiview High Efficiency Video Coding. An advanced WPP method is proposed to achieve higher intra-frame parallelism. • The proposed method is compatible with that of the SIMD acceleration method. • The proposed method can achieve real-time decompression of MV-HEVC with three views. [ABSTRACT FROM AUTHOR]

An important concept in finite state machine based testing is synchronization which is used to initialize an implementation to a particular state. Usually, synchronizing sequences are used for this purpose and the length of the sequence used is important since it determines the cost of the initialization process. Unfortunately, the shortest synchronization sequence problem is NP-Hard. Instead, heuristics are used to generate short sequences. However, the cubic complexity of even the fastest heuristic algorithms can be a problem in practice. In order to scale the performance of the heuristics for generating short synchronizing sequences, we propose algorithmic improvements together with a parallel implementation of the cheapest heuristics existing in the literature. To identify the bottlenecks of these heuristics, we experimented on random and slowly synchronizing automata. The identified bottlenecks in the algorithms are improved by using algorithmic modifications. We also implement the techniques on multicore CPUs and Graphics Processing Units (GPUs) to take benefit of the modern parallel computation architectures. The sequential implementation of the heuristic algorithms are compared to our parallel implementations by using a test suite consisting of 1200 automata. The speedup values obtained depend on the size and the nature of the automaton. In our experiments, we observe speedup values as high as 340x by using a 16-core CPU parallelization, and 496x by using a GPU. Furthermore, the proposed methods scale well and the speedup values increase as the size of the automata increases. • We propose algorithmic improvements together with an efficient parallelization approach for synchronizing sequence heuristics. • We experimented on random and slowly synchronizing automata. • We implement the proposed techniques on multicore CPUs and Graphics Processing Units (GPUs) to take benefit of the modern parallel architectures. • With the proposed techniques, we observe speedup values as high as 340x by using a 16-core CPU parallelization, and 496x by using a GPU. • The proposed methods scale well and the speedup values increase as the size of the automata increases. [ABSTRACT FROM AUTHOR]

Basic Linear Algebra Subprograms (BLAS) are the building blocks for various numerical algorithms and are widely used in scientific computations. However, some linear algebra applications need more precision than the standard double precision available in most existing BLAS libraries. In this paper, we implement and evaluate multiple-precision scalar and vector BLAS functions on graphics processing units (GPUs). We use the residue number system (RNS) to represent arbitrary length floating-point numbers. The non-positional nature of RNS enables parallelism in multiple-precision arithmetic and makes RNS a good tool for high-performance computing applications. We first present new data-parallel algorithms for multiplying and adding RNS-based floating-point representations. Next, we suggest algorithms for multiple-precision vectors specially designed for parallel computations on GPUs. Using these algorithms, we develop and evaluate four GPU-accelerated multiple-precision BLAS functions, ASUM, DOT, SCAL, and AXPY. It is shown through experiments that in many cases, the implemented functions achieve significantly better performance compared to existing multiple-precision software for CPU and GPU. • Residue number system enables parallelism in arithmetic with multiple precision. • New algorithms for arbitrary length floating-point numbers are presented. • Multiple-precision ASUM, DOT, SCAL, and AXPY are implemented using CUDA and evaluated. • We show that multiple-precision BLAS can be accelerated using GPU. [ABSTRACT FROM AUTHOR]

This paper introduces a platform to support serverless computing for scalable event-driven data processing that features a multi-level elasticity approach combined with virtualization of GPUs. The platform supports the execution of applications based on Docker containers in response to file uploads to a data storage in order to perform the data processing in parallel. This is managed by an elastic Kubernetes cluster whose size automatically grows and shrinks depending on the number of files to be processed. To accelerate the processing time of each file, several approaches involving virtualized access to GPUs, either locally or remote, have been evaluated. A use case that involves the inference based on deep learning techniques on transthoracic echocardiography imaging has been carried out to assess the benefits and limitations of the platform. The results indicate that the combination of serverless computing and GPU virtualization introduce an efficient and cost-effective event-driven accelerated computing approach that can be applied for a wide variety of scientific applications. • Several GPU virtualization approaches are assessed in an on-premises serverless computing scenario. • RCUDA is employed to provide multi-tenant remote access to GPU for function invocation acceleration. • A use case based on deep learning techniques for image classification is integrated into such a serverless platform. • Serverless computing and GPU virtualization provides cost-effective event-driven accelerated computing. [ABSTRACT FROM AUTHOR]

The Graphics Processing Unit (GPU) is now used extensively for general purpose GPU programming (GPGPU), allowing for greater exploitation of the multi-core model across many application domains. This is particularly true in cloud/edge/fog computing, where multiple GPU enabled servers support many different end user services. This move away from the naturally parallel domain of graphics can incur significant performance issues. Unlike the CPU, code that is hindered from execution due to blocking/waiting on the GPU can affect thousands of threads, rendering the advantages of a GPU irrelevant and reducing a highly parallel environment down to a serial one in the worst case. In this paper we present a solution that minimises blocking/waiting in GPGPU computing using a contention manager that offsets memory conflicts across threads through thread re-ordering. We consider conflicts of memory not only to avoid corruption (standard for transactional memory) but also in the semantic layer of application logic (e.g., enforcing ordering to ensure money drawn from bank account occurs after all deposits). We demonstrate how our approach is successful across a number of industry benchmarks and compare our approach to the only other related solution. We also demonstrate that our approach is scalable in terms of thread numbers (a key requirement on the GPU). We believe this is the first work of its kind demonstrating a generalised conflict and semantic contention manager suitable for the scale of parallel execution found on a GPU. • Generalised, automated, solution to minimise application conflicts of general programming on GPU. • Novel transactional memory algorithm for highly parallel architectures (GPU). • Benchmarked against related work. • Parallel implementation providing scalable performance of conflict resolution. [ABSTRACT FROM AUTHOR]

The performance of parallel algorithms is often inconsistent with their preliminary theoretical analyses. Indeed, the difference is increasing between the ability to theoretically predict the performance of a parallel algorithm and the results measured in practice. This is mainly due to the accelerated development of advanced parallel architectures, whereas there is still no agreed model for parallel computation, which has implications for the design of parallel algorithms and for the manner in which parallel programming should be taught. In this study, we examined the practical performance of Cormen's Quicksort parallel algorithm. We determined the performance of the algorithm with different parallel programming approaches and examine the capacity of theoretical performance analyses of the algorithm for predicting the actual performance. This algorithm is used for teaching theoretical and practical aspects of parallel programming to undergraduate students. We considered the pedagogic implications that may arise when the algorithm is used as a learning resource for teaching parallel programming. • Performance analysis of Cormen's parallel Quicksort algorithm. • Comparing the performance of various implementations of Cormen's algorithm. • Examination of the theoretical performance prediction of Coremen's algorithm. [ABSTRACT FROM AUTHOR]

Three parallel sorting applications and two list output protocols for the first phase of an external sort execute on a fine-grained many-core processor array that contains no algorithm-specific hardware acting as a co-processor with a variety of array sizes. Results are generated using a cycle-accurate model based on measured data from a fabricated many-core chip, and simulated for different processor array sizes. The data shows most energy efficient first-phase many-core sort requires over 65 × lower energy than GNU C++ standard library sort performed on an Intel laptop-class processor and over 105 × lower energy than a radix sort running on an Nvidia GPU. In addition, the highest first-phase throughput many-core sort is over 9.8 × faster than the std::sort and over 14 × faster than the radix sort. Both phases of a 10 GB external sort require 6.2 × lower energy × time energy delay product than the std::sort and over 13 × lower energy × time than the radix sort. • Many-core processors can serve as a high-performance energy-efficient co-processor. • A massive array of simple processors can efficiently perform large modular sorts. • These sorts easily scale with different sized general purpose processing arrays. • A first-phase many-core sort requires 105x less energy than a radix sort on a GPU. • A 10 GB many-core external sort requires 6.2x lower EDP than std::sort on a laptop. [ABSTRACT FROM AUTHOR]

Encryption is an important technique to improve information security for many real-world applications. The Advanced Encryption Standard (AES) is a widely-used efficient cryptographic algorithm. Although AES is fast both in software and hardware, it is time-consuming to do data encryption especially for large amount of data. Therefore, it is a lasting effort to accelerate AES operations. This paper presents SW-AES, a parallel AES implementation on the Sunway TaihuLight, one of the fastest supercomputers in the world that takes the SW26010 processor as the basic building block. According to the architectural features of SW26010, SW-AES exploits parallelism from different levels, including (1) inter-CPE (Computing Processing Element) data parallelism that distributes tasks among the 256 on-chip CPEs, (2) intra-CPE data parallelism enabled by the Single-Instruction Multiple-Data (SIMD) instructions inside each CPE, and (3) instruction-level parallelism that pipelines memory access and the computation. In addition, corresponding to the two application scenarios, SW-AES presents scalable ways to efficiently run AES on many nodes. As a result, SW-AES can gain a maximum throughput of 13.50 GB/s on a single SW26010 node, which is 216.23 × higher than the latest parallel AES implementation on the Sunway TaihuLight, and about 37.3% higher than the latest AES implementation on the GTX 480 GPU. When running on 1024 computing nodes with each one processing 1 GB data, SW-AES can achieve a throughput of 13819.25 GB/s. On the contrast, only a throughput of 63.91 GB/s can be achieved by the latest related work on the Sunway TaihuLight. • A data layout enabling SIMD operations inside one Computing Processor Element. • An S-Box lookup strategy improving the performance of nonvectorized memory access. • A data parallelism to fully use the 256 Computing Processor Elements on a chip. • New mechanisms to scale AES operations of different scenarios to many nodes. [ABSTRACT FROM AUTHOR]

A wealth of important scientific and engineering applications are configured for use on high performance computing architectures using functionality found in the MPI specification. This specification provides application developers with a straightforward means for implementing their ideas for execution on distributed-memory parallel processing computers. OpenMP directives provide a means for operating on shared-memory regions of those computers. With the advent of machines composed of many-core processors, the strict synchronisation required by the bulk synchronous parallel (BSP) communication model can hinder performance increases. This is due to the complexity to handle load imbalances, to reduce serialisation imposed by blocking communication patterns, to overlap communication with computation and, finally, to deal with increasing memory overheads. The MPI specification provides advanced features such as non-blocking calls or shared memory to mitigate some of these factors. However, applying these features efficiently usually requires significant changes on the application structure. Task parallel programming models are being developed as a means of mitigating the abovementioned issues but without requiring extensive changes on the application code. In this work, we present a methodology to develop hybrid applications based on tasks called hierarchical domain over-decomposition with tasking (HDOT). This methodology overcomes most of the issues found on MPI-only and traditional hybrid MPI+OpenMP applications. However, by emphasising the reuse of data partition schemes from process-level and applying them to task-level, it enables a natural coexistence between MPI and shared-memory programming models. The proposed methodology shows promising results in terms of programmability and performance measured on a set of applications. • We present HDOT, a top-down approach for productive, hybrid programming. • We identify common patterns for data partitioning, distribution and reduction. • We examine its applicability on three applications. [ABSTRACT FROM AUTHOR]

The exponential growth of next generation sequencing (NGS) data has put forward the challenge for its storage as well as its efficient and faster analysis. Storing the entire amount of data for a particular experiment and its alignment to the reference genome is an essential step for any quantitative analysis of NGS data. Here, we introduce streaming access technique ' ParStream-seq ' that splits the bulk sequence data, accessed from a remote repository into short manageable packets followed by executing their alignment process in parallel in each of the compute core. The optimal packet size with fixed number of reads is determined in the stream that maximizes system utilization. Result shows a reduction in the execution time and improvement in the memory footprint. Overall, this streaming access technique provides means to overcome the hurdle of storing the entire volume of sequence data corresponding to a particular experiment, prior to its analysis. • Introduced a sequence streaming protocol called ParStream-seq which splits and access the bulk sequence data. • To overcome the hurdle of storing the entire volume of NGS data corresponding to a particular experiment. • Determined the 'optimal packet size' with a fixed number of reads and optimal number of sequence splits for streaming. • It facilitates parallel execution of alignment process and stores the results in the Hadoop Distributed File system (HDFS). [ABSTRACT FROM AUTHOR]

This paper describes a unified view of parallel evolutionary algorithms for multi-objective optimization problems. The parallel optimization algorithms are detailed from both design and implementation aspects. The proposed taxonomy is based on three hierarchical parallel models. Moreover, various parallel architectures are taken into account. The performance assessment issue of parallel multi-objective evolutionary algorithms (MOEA) is also presented. This work can be extended to any population-based metaheuristics such as particle swarm and scatter search. • The main highlights of this paper is the development of a unified view of parallel multi-objective evolutionary algorithms in terms of design and implementation. • The parallel models have been analyzed according to different parallel architectures. • The different parallel models have been illustrated. • The paper is also a guideline to researchers and engineers to design and implement efficient and effective parallel evolutionary algorithms for multi-objective optimization. [ABSTRACT FROM AUTHOR]

To overcome the high computational cost associated with the high-dimensional digital image descriptor matching, this paper presents a set of integrated parallel algorithms for the construction of K -dimensional tree (KD-tree) and P approximate nearest neighbor search (P -ANNS) on the modern massively parallel architectures (MPA). To improve the runtime performance of the P -ANNS, we propose an efficient sliding window for a parallel buffered P -ANNS on KD-tree to mitigate the high cost of global memory accesses. When applied to high dimensional real-world image descriptor datasets, the proposed KD-tree construction and the buffered P -ANNS algorithms are of comparable matching quality to the traditional sequential counterparts on CPU, while outperforming their serial CPU counterparts by speedup factors of up to 17and 163, respectively. The algorithms are also studied for the performance impact factors to obtain the optimal runtime configurations for various datasets. Moreover, we verify the features of the parallel algorithms on typical 3D image matching scenarios. With the classical local image descriptor signature of histograms of orientations (SHOT) datasets, the parallel KD-tree construction and image descriptor matching can achieve up to 11 and 138-fold speedups, respectively. • High dimensional datasets: KD-tree construction and P-ANNS are fine-grain parallelized. • KD-Tree Structure: for parallel search on the GPU, search points are all located in the leaf nodes. • Hybrid Search: linear search (in the leaf node) is traded off with the nonlinear (tree backtracking). • Priority Queue: unproductive nodes are avoided, by replacing normal queue with priority queue. • Sliding Window: Speed performance of P-ANNS, is achieved with sliding window parallel buffer. [ABSTRACT FROM AUTHOR]

Nowadays, high-end Systems consist of thousands of individual devices which are in general heterogeneous. Grid computing environments are an example of high-end systems which are composed of many diverse and heterogeneous resources distributed within multiple geographical areas. The performance of such systems depends considerably on job scheduling and resource allocation algorithms. Indeed, to improve the global throughput of these environments, effective and efficient load balancing algorithms are fundamentally important. In this paper, we propose a completely distributed formal model for the description of grid architecture. Our model, is then parameterized to describe different job-scheduling algorithms in a completely parallel architecture. In particular, we focus on the modeling and description of distributed load-balancing algorithms. To reach this purpose, we define a set of parallel schedulers communicating together to achieve a given load-balancing policy. To show the applicability of our approach, we propose to specify and compare different well-known job-scheduling policies in grid environments. The formal verification of different properties of the studied protocols has been performed automatically using Model-checking and a set of performance analysis results are also provided. • A generic formal model for the description of a Grid architecture as a component-based system. A completely parallel model built as a set of communicating local-schedulers. • A completely distributed model built as a composition of a set of local schedulers communicating via a set of connectors (interactions). We believe that any distributed job-scheduling strategy could be easily implemented using interactions and priorities between these interactions. • The model is adapted to describe a set of well-known load-balancing protocols • We have conducted several formal verification experiments to prove a set of properties over the modeled protocols • We have performed a series of experiments to evaluate, analyze and compare the performance of the modeled protocols under a set of real-time executions for different configurations and metrics. [ABSTRACT FROM AUTHOR]

Nested loops are main source of the parallelism in many scientific applications. Partitioning the iteration space of nested loops with data dependencies into tiles and assigning them to processing nodes for parallel execution is essential for achieving high performance. Although most of the previous work focused on tiling on fully connected homogeneous distributed systems, some studies have been devoted to tiling on partially connected distributed systems. In this paper, we address the parallelization of perfectly nested loops with dependencies on partially connected heterogeneous distributed systems and present a topology and computational-power aware tile mapping. This work aims to take into account not only the node's computational power when tiling iteration space of nested loops but also the exploitation of the network topology when mapping tiles to processing nodes. This approach allows minimizing the parallel execution time by improving the load balancing and minimizing the communication costs. We demonstrate the performance of proposed method by comparing it with the computational-power aware tile mapping and the topology aware tile mapping. The experimental results show that the proposed method improves the parallel execution time by up to 62% and 28% compared with the computational-power aware tile mapping and the topology aware tile mapping, respectively. • The parallelization problem of perfectly nested loop with dependencies is addressed. • A topology and computational-power aware tile mapping is proposed. • A theoretical model is developed to estimate the parallel execution time. • A genetic algorithm is extended to find the near-optimal tile sizes. • The experiments are conducted on several distributed systems and analyzed the results. [ABSTRACT FROM AUTHOR]

Verbal repetition requires the coordination of auditory, memory, linguistic, and motor systems. To date, the basic dynamics of neural information processing in this deceptively simple behavior are largely unknown. Here, we examined the neural processes underlying verbal repetition using focal interruption (electrocortical stimulation) in 58 patients undergoing awake craniotomies, and neurophysiological recordings (electrocorticography) in 8 patients while they performed a single word repetition task. Electrocortical stimulation revealed that sub-components of the left peri-Sylvian network involved in single word repetition could be differentially interrupted, producing transient perceptual deficits, paraphasic errors, or speech arrest. Electrocorticography revealed the detailed spatio-temporal dynamics of cortical activation, involving a highly-ordered, but overlapping temporal progression of cortical high gamma (75-150Hz) activity throughout the peri-Sylvian cortex. We observed functionally distinct serial and parallel cortical processing corresponding to successive stages of general auditory processing (posterior superior temporal gyrus), speech-specific auditory processing (middle and posterior superior temporal gyrus), working memory (inferior frontal cortex), and motor articulation (sensorimotor cortex). Together, these methods reveal the dynamics of coordinated activity across peri-Sylvian cortex during verbal repetition. [ABSTRACT FROM AUTHOR]

Abstract The great potential of computational diffusion MRI (dMRI) relies on indirect inference of tissue microstructure and brain connections, since modelling and tractography frameworks map diffusion measurements to neuroanatomical features. This mapping however can be computationally highly expensive, particularly given the trend of increasing dataset sizes and the complexity in biophysical modelling. Limitations on computing resources can restrict data exploration and methodology development. A step forward is to take advantage of the computational power offered by recent parallel computing architectures, especially Graphics Processing Units (GPUs). GPUs are massive parallel processors that offer trillions of floating point operations per second, and have made possible the solution of computationally-intensive scientific problems that were intractable before. However, they are not inherently suited for all problems. Here, we present two different frameworks for accelerating dMRI computations using GPUs that cover the most typical dMRI applications: a framework for performing biophysical modelling and microstructure estimation, and a second framework for performing tractography and long-range connectivity estimation. The former provides a front-end and automatically generates a GPU executable file from a user-specified biophysical model, allowing accelerated non-linear model fitting in both deterministic and stochastic ways (Bayesian inference). The latter performs probabilistic tractography, can generate whole-brain connectomes and supports new functionality for imposing anatomical constraints, such as inherent consideration of surface meshes (GIFTI files) along with volumetric images. We validate the frameworks against well-established CPU-based implementations and we show that despite the very different challenges for parallelising these problems, a single GPU achieves better performance than 200 CPU cores thanks to our parallel designs. Highlights • The computational power offered by GPUs is used to accelerate the analysis of dMRI. • We present a generic and flexible parallel framework for microstructure modelling on GPUs. • And also a framework for performing probabilistic tractography and generating connectomes on GPUs. • A single GPU achieves better performance than 200 CPU cores with our frameworks. [ABSTRACT FROM AUTHOR]

Highlights • Study of comparable corpora(CC) for extracting parallel information. • Generative model for extracting parallel fragments of CC without need of initial seed. • Enhancing a SMT system using extracted parallel fragments from CC. Abstract Although parallel corpora are essential language resources for many natural language processing tasks, they are rare or even not available for many language pairs. Instead, comparable corpora are widely available and contain parallel fragments of information that can be used in applications like statistical machine translation systems. In this research, we propose a generative latent Dirichlet allocation based model for extracting parallel fragments from comparable documents without using any initial parallel data or bilingual lexicon. The experimental results show significant improvement if the extracted fragments generated by the proposed method are used for augmenting an existing parallel corpus in an statistical machine translation system. According to the human judgment, the accuracy of the proposed method for an English-Persian task is about 59.7%. Also, the out of vocabulary error rate for the same task is reduced by 28%. [ABSTRACT FROM AUTHOR]

Abstract The scalable analysis of crowdsourced data repositories and streams has quickly become a critical experimental asset in multiple fields. It enables the systematic aggregation of otherwise disperse data sources and their efficient processing using significant amounts of computational resources. However, the considerable amount of crowdsourced social data and the numerous criteria to observe can limit analytical off-line and on-line processing due to the intrinsic computational complexity. This paper demonstrates the efficient parallelisation of profiling and recommendation algorithms using tourism crowdsourced data repositories and streams. Using the Yelp data set for restaurants, we have explored two different profiling approaches: entity-based and feature-based using ratings, comments, and location. Concerning recommendation, we use a collaborative recommendation filter employing singular value decomposition with stochastic gradient descent (SVD-SGD). To accurately compute the final recommendations, we have applied post-recommendation filters based on venue suitability, value for money, and sentiment. Additionally, we have built a social graph for enrichment. Our master–worker implementation shows super-linear scalability for 10, 20, 30, 40, 50, and 60 concurrent instances. Highlights • Parallel data stream algorithm. • Scalable Recommendation Engine. • Profiling and Recommendation algorithms using scalable data analytics. • Post-Recommendations filtering to accurate the final recommendations. [ABSTRACT FROM AUTHOR]

Highlights • Retention was measured for three types of a serial pattern elements. • Male and female rats had different forgetting curves for some elements. • Elements learned via different mechanisms were forgotten at different rates. • Elements that were learned slower to asymptote were forgotten faster. • Multiple memory systems in serial memory can be dissociated via forgetting curves. Abstract Serial pattern learning is a model paradigm for studying parallel-processing in complex learning in rats. The current experiment extends the paradigm to the study of sequential memory by examining forgetting curves for the component element types that make up a serial pattern. Adult male and female rats were trained in a serial multiple choice (SMC) task in which rats learned a serial pattern of nose-poke responses in a circular array of 8 receptacles mounted on the walls of an octagonal operant chamber. The pattern was 123–234–345–456–567–678–781–818, where digits represent the clockwise positions of successive correct receptacles. Previous work has shown that chunk-boundary elements (the first element of each 3-element chunk), within-chunk elements (the second and third elements in all but the last chunk), and the violation element (the last element of the pattern) are learned via different cognitive mechanisms. After each rat was trained to an 85% correct performance criterion on the violation element, we then assessed serial pattern retention at 24-h, 2-week, and 4-week retention intervals. For chunk-boundary and within-chunk elements, forgetting was observed only at the 4-week retention interval. Sex differences were observed; females performed better than males on within-chunk elements at 24-h and 4-week retention intervals. For the violation element, significant forgetting was observed earlier at the 2-week retention interval as well as at the 4-week retention interval. Thus, pattern elements that were learned slower were forgotten faster. The experiment provides a proof of concept for evaluating forgetting curves separately for the multiple memory systems rats appear to employ concurrently in this paradigm, a method that may prove useful in characterizing the impact of relevant neurobiological manipulations on forgetting in multiple sequential memory systems. [ABSTRACT FROM AUTHOR]

• Discrete digit naming was a unique predictor of discrete naming of high-frequency 1- and 2-character word reading. • Serial digit naming was a unique predictor of discrete naming of low-frequency 1-character word reading and high-frequency 2-character word reading. • Serial digit naming predicted serial reading fluency of only high-frequency words. • Findings provide support of the cascaded processing hypothesis. Recent studies have suggested that—beyond automaticity and prosody—reading fluency involves parallel processing of adjacent items presented in a sequence, termed "cascaded processing." To date, most studies examining cascaded processing have been conducted in alphabetic orthographies. Thus, the purpose of this study was to examine the cascaded processing hypothesis in Chinese. A total of 119 Grade 1 Chinese children (61 boys and 58 girls; M age = 7.30 years, SD = 0.31) were assessed on serial and discrete naming of digits as well as on serial and discrete naming of high-frequency one- and two-character words and low-frequency one-character words presented with pinyin. Results of hierarchical regression analyses showed, first, that serial digit naming was a unique predictor of discrete naming of low-frequency one-character words and two-character words, but not of high-frequency one-character words. Second, serial digit naming was a unique predictor of reading of high-frequency one- and two-character word reading after controlling for discrete word reading. These findings suggest that Chinese first graders process high-frequency characters holistically (similar to simple digits), which then facilitates parallel processing of multiple stimuli when they are presented in a sequence. [ABSTRACT FROM AUTHOR]

For large-scale sparse matrices, SpMV cannot be processed on GPU using the common storage formats because of the memory limitation. In addition, the parallel effect is poor using general formats for the sparse matrices with extremely uneven distribution of non-zero elements, which leads to performance deterioration. This paper presents an optimal partitioning strategy based on the distribution of non-zero elements in a sparse matrix to improve the performance of SpMV, and uses a hybrid format, which mixes CSR and ELL formats, to store the blocks partitioned from the sparse matrix. The hybrid blocked format has better compression effect and more uniform distribution of non-zero elements, which can be suitable for more types of sparse matrices. Our partitioning strategy is proven to be optimal, which can yield the minimum parallel execution time on GPU. [ABSTRACT FROM AUTHOR]

We review some of the recent advances in level-set methods and their applications. In particular, we discuss how to impose boundary conditions at irregular domains and free boundaries, as well as the extension of level-set methods to adaptive Cartesian grids and parallel architectures. Illustrative applications are taken from the physical and life sciences. Fast sweeping methods are briefly discussed. [ABSTRACT FROM AUTHOR]

In the rapidly expanding field of parallel processing, job schedulers are the “operating systems” of modern big data architectures and supercomputing systems. Job schedulers allocate computing resources and control the execution of processes on those resources. Historically, job schedulers were the domain of supercomputers, and job schedulers were designed to run massive, long-running computations over days and weeks. More recently, big data workloads have created a need for a new class of computations consisting of many short computations taking seconds or minutes that process enormous quantities of data. For both supercomputers and big data systems, the efficiency of the job scheduler represents a fundamental limit on the efficiency of the system. Detailed measurement and modeling of the performance of schedulers are critical for maximizing the performance of a large-scale computing system. This paper presents a detailed feature analysis of 15 supercomputing and big data schedulers. For big data workloads, the scheduler latency is the most important performance characteristic of the scheduler. A theoretical model of the latency of these schedulers is developed and used to design experiments targeted at measuring scheduler latency. Detailed benchmarking of four of the most popular schedulers (Slurm, Son of Grid Engine, Mesos, and Hadoop YARN) is conducted. The theoretical model is compared with data and demonstrates that scheduler performance can be characterized by two key parameters: the marginal latency of the scheduler t s and a nonlinear exponent α s . For all four schedulers, the utilization of the computing system decreases to <10% for computations lasting only a few seconds. Multi-level schedulers (such as LLMapReduce) that transparently aggregate short computations can improve utilization for these short computations to >90% for all four of the schedulers that were tested. [ABSTRACT FROM AUTHOR]

Precise and fast shape matching and retrieval from very large datasets is a challenging task because of the existence of many distortions such as noise, occlusion and affine distortions. In this paper, we aim to propose a time-saving and effective shape matching and retrieval framework, that employs pruning which will enable online shape retrieval from extremely large datasets. First, using a hierarchical tree-based structure supporting parallel processing and efficient feature descriptors, irrelevant shapes are pruned and a subset of shapes relevant to the query is selected, then using more sophisticated feature descriptors, accurate retrieval is performed. Contour representation of an object is considered as most significant visual shape similarity measure by the humans. Using boundary information, we generate two simplified and efficient feature descriptors for fast pruning, and a sophisticated feature descriptor for effective and accurate retrieval. Tests performed on standard datasets unveil that the proposed technique is computationally more efficient than the state-of-the-art techniques while maintaining comparable matching and retrieval performance. Its performance is scalable for huge datasets and is robust against affine transformations, articulations and occlusion. [ABSTRACT FROM AUTHOR]

Image features are widely used for object identification in many situations, including interpretation of data containing natural scenes captured by unmanned aerial vehicles. This paper presents a parallel framework to extract additive features (such as color features and histogram of oriented gradients) using the processing power of GPUs and multicore CPUs to accelerate the algorithms with the OpenCL language. The resulting features are available in device memory and then can be fed into classifiers such as SVM, logistic regression and boosting methods for object recognition. It is possible to extract multiple features with better performance. The GPU accelerated image integral algorithm speeds up computations up to 35x when compared to the single-thread CPU implementation in a test bed hardware. The proposed framework allows real-time extraction of a very large number of image features from full-HD images (better than 30 fps) and makes them available for access in coalesced order by GPU classification algorithms. [ABSTRACT FROM AUTHOR]

Limitations of I/O bandwidth and latency are a serious burden for many data intensive algorithms. This is even more noticeable in distributed heterogeneous clusters that heavily utilize GPU processors, where communication costs and limitation of memory play crucial role. Lightweight lossless compression methods are often applied to cope with those limitations. In this paper we investigate new approaches to parallel lossless lightweight compression methods based on fixed-length minimum bit encoding for GPU processors. By developing new memory organization and by utilizing various inter thread and inter warp communication abilities, we have proposed algorithms which suit GPU architecture better. As a result we have significantly improved compression ratio and bandwidths. This allows for many new applications in computational clusters as well as in computational algorithms. Our claims are supported by tests conducted using simulated data and TPC-H database benchmarking tools. [ABSTRACT FROM AUTHOR]

The increasing integration of computing into the physical systems we rely on everyday motivates the need to more easily marry advanced control theory, which is used to control these systems, with the computing platforms used to implement the controllers. This article explores one path of easing this integration using reconfigurable hardware technology, and discusses practical system-level details that must be addressed for integrating our idea into real-world systems. We present a software configurable and parallelized coprocessor architecture for LQR control that can control physical processes representable by a linear state-space model. Our proposed architecture has distinct advantages over purely software or purely hardware approaches. It differs from other hardware controllers in that it is not hardwired to control one or a small range of plant types (e.g. only electric motors). Via software, an embedded systems engineer can easily reconfigure the controller to suit a wide range of control applications that can be represented as a state-space model. One goal of our approach is to support a design methodology to help bridge the gap between controls and embedded system software engineering. Control of the well-understood inverted pendulum on a cart is used as an illustrative example of how the proposed hardware accelerator architecture supports our envisioned design methodology for helping bridge this gap. Additionally, we explore the design space of our co-processor’s parallel architecture in terms of computing speed and resource utilization. Our performance results show a 3.4 to 100 factor speedup over a 666 MHz embedded ARM processor, for plants that can be represented by 4 to 128 states, respectively. This article concludes with a discussion of the practical integration details required for interfacing the controller with a real inverted pendulum–cart system. [ABSTRACT FROM AUTHOR]

Prevalent hardware trends towards parallel architectures and algorithms create a growing demand for graduate students familiar with the programming of concurrent software. However, learning parallel programming is challenging due to complex communication and memory access patterns as well as the avoidance of common pitfalls such as dead-locks and race conditions. Hence, the learning process has to be supported by adequate software solutions in order to enable future computer scientists and engineers to write robust and efficient code. This paper discusses a selection of well-known parallel algorithms based on C++11 threads, OpenMP, MPI, and CUDA that can be interactively embedded in an HPC or parallel computing lecture using a unified framework for the automated evaluation of source code—namely the “System for AUtomated Code Evaluation” (SAUCE). SAUCE is free software licensed under AGPL-3.0 and can be downloaded at https://github.com/moschlar/SAUCE free of charge. [ABSTRACT FROM AUTHOR]