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Low‐temperature polycrystalline silicon (LTPS) thin‐film transistor devices can be used as core components of pixel driving circuits for active matrix organic light‐emitting displays （AMOLED）. Poly silicon (P‐Si) film and device performance directly affects the display effect. This paper investigates polysilicon grain boundary reduction for LTPS devices on PI substrates, exploring the effects of grain boundary reduction on LTPS devices and image sticking. Reduction of polysilicon grain boundaries through optimization of a‐Si deposition process, a‐Si two‐step deposition and excimer laser annealing (ELA) doublescan process, ELA double‐scan process reduces grain boundaries by 67 %. We prepared LTPS devices with thinner gate interlayers (GI) based on P‐Si grain boundary reduction, LTPS devices with positive threshold voltage bias and increased mobility, AMOLED displays with thinner GI can have 23% better image sticking. [ABSTRACT FROM AUTHOR]

This paper reports the development and integration of (Poly‐Si/Air)n Distributed BRAGG Reflectors (DBR) in a MOEMS Fabry‐Pérot‐Interferometer (FPI) concept. The realized reflectors constitute a promising and resource‐efficient alternative to complex Ion‐Assisted Deposition based DBRs while maintaining their advantages. Compared to state of the art MOEMS FPIs the (Poly‐Si/Air)n DBRs can be integrated into two moveable reflector carriers based on two individually fabricated wafers which are bonded. The (Poly‐Si/Air)n DBRs are investigated as (HL) and (HL)2 reflector stacks showing a reflectance above 91% within the wavelength range of 2.8–5.7 μm. © 2023 The Authors. IEEJ Transactions on Electrical and Electronic Engineering published by Institute of Electrical Engineer of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

The discovery of ferroelectricity in hafnia-based materials has revitalized interest in realizing ferroelectric field-effect transistors (FeFETs) due to its compatibility with modern microelectronics. Furthermore, low-temperature processing by atomic layer deposition offers promise for realizing monolithic three-dimensional (M3D) integration toward energy- and area-efficient computing paradigms. However, integrating ferroelectrics with channel materials in FeFETs for M3D integration remains challenging due to the dual requirement of a high-quality ferroelectric-channel interface and low-power operation, all while maintaining back-end-of-line (BEOL)-compatible fabrication temperatures. Recent studies on 2D semiconductors and metal oxide channels highlight these challenges. Polycrystalline silicon (poly-Si), a channel material long integrated into the semiconductor industry, presents a promising alternative; however, its high fabrication temperature has hindered its applications to M3D integration. To overcome this challenge, we demonstrates a BEOL-compatible FeFET platform using poly-Si channels fabricated via locally-confined laser thermal processing and hafnia-based ferroelectrics by low-temperature atomic layer deposition with wafer-scale uniformity. The local nature of the laser processing mitigates the trade-off between the high-temperature crystallization for the quality of the interface and BEOL thermal budget constraints. The laser-processed FeFETs boast the largest effective memory widow for all BEOL-compatible FeFETs. Moreover, the fabricated FeFETs are integrated into wafer-scale synaptic arrays for neuromorphic computing, achieving record-high energy efficiency. Therefore, this work establishes a promising BEOL-compatible FeFET materials platform toward M3D integration., (© 2024 The Author(s). Small published by Wiley‐VCH GmbH.)

Full-area passivating contacts based on SiO x /poly-Si stacks are key for the new generation of industrial silicon solar cells substituting the passivated emitter and rear cell (PERC) technology. Demonstrating a potential efficiency increase of 1 to 2% compared to PERC, the utilization of n-type wafers with an n-type contact at the back and a p-type diffused boron emitter has become the industry standard in 2024. In this work, variations of this technology are explored, considering p-type passivating contacts on p-type Si wafers formed via a rapid thermal processing (RTP) step. These contacts could be useful in conjunction with n-type contacts for realizing solar cells with passivating contacts on both sides. Here, a particular focus is set on investigating the influence of the applied thermal treatment on the interfacial silicon oxide (SiO x ) layer. Thin SiO x layers formed via ultraviolet (UV)-O 3 exposure are compared with layers obtained through a plasma treatment with nitrous oxide (N 2 O). This process is performed in the same plasma enhanced chemical vapor deposition (PECVD) chamber used to grow the Si-based passivating layer, resulting in a streamlined process flow. For both oxide types, the influence of the RTP thermal budget on passivation quality and contact resistivity is investigated. Whereas the UV-O 3 oxide shows a pronounced degradation when using high thermal budget annealing ( T > 860 °C), the N 2 O-plasma oxide exhibits instead an excellent passivation quality under these conditions. Simultaneously, the contact resistivity achieved with the N 2 O-plasma oxide layer is comparable to that yielded by UV-O 3 -grown oxides. To unravel the mechanisms behind the improved performance obtained with the N 2 O-plasma oxide at high thermal budget, characterization by high-resolution (scanning) transmission electron microscopy (HR-(S)TEM), X-ray reflectometry (XRR) and X-ray photoelectron spectroscopy (XPS) is conducted on layer stacks featuring both N 2 O and UV-O 3 oxides after RTP. A breakup of the UV-O 3 oxide at high thermal budget is observed, whereas the N 2 O oxide is found to maintain its structural integrity along the interface. Furthermore, chemical analysis reveals that the N 2 O oxide is richer in oxygen and contains a higher amount of nitrogen compared to the UV-O 3 oxide. These distinguishing characteristics can be directly linked to the enhanced stability exhibited by the N 2 O oxide under higher annealing temperatures and extended dwell times.

This study focused on optimizing the high-temperature crystallization annealing process in the production of TOPCon solar cells to enhance power conversion efficiency. The annealing process is employed to transform amorphous silicon into polycrystalline silicon (Poly-Si). Furthermore, during this annealing process, phosphorus atoms can form Si–P bonds to achieve effective doping in the Poly-Si layer. The experimental results indicated that, under high-temperature conditions, phosphorus atoms in the Poly-Si layer near the crystalline silicon wafer surface crossed the tunneling layer and infiltrated into the silicon substrate. Intensive inward diffusion resulted in the accumulation of phosphorus close to the wafer surface. The loss of numerous phosphorus atoms in the Poly-Si layer and the accumulation of phosphorus in the wafer readily lead to the formation of an undesirable N−/N+ high-low junction, which is detrimental to carriers' output. However, the annealing condition affects the crystallinity of the Poly-Si layer, which is crucial to providing an excellent passivation effect. This study achieved the optimal annealing conditions for the current N-type TOPCon solar cell production process by adjusting the annealing temperature and crystallization time. Ensuring Poly-Si crystallization and minimizing phosphorus inward diffusion resulted in an approximate 0.1% abs. improvement in cells' power conversion efficiency. [Display omitted] • The annealing process was optimized to reduce the phosphorus inward diffusion. • The N−/N+ high-low junctions inside the substrate were eliminated. • Barrier was decreased by the optimization, leading to high efficient electron transportation. • The efficiency of solar cells was increased by approximate 0.1% abs.. [ABSTRACT FROM AUTHOR]

The objectives of this study are to explore the activation ratios of implanted phosphorus dopants in polycrystalline silicon (poly-Si), and to reveal the role of grain boundary segregation in incomplete activation using atom probe tomography (APT) and differential Hall effect metrology (DHEM). After implantation and rapid thermal annealing, the results of APT revealed pronounced segregation toward grain boundaries that provides rapid diffusion paths for phosphorus. Peak concentrations of phosphorus segregations in the grain boundaries of the regrown and non-regrown regions were measured to be 4.38E21 and 2.17E21 atoms/cm³ that correspond to activation ratios of 6 % and 1 %, respectively. In contrast, phosphorus concentrations within grain interiors were found to be 6.86E20 and 1.72E19 atoms/cm³, corresponding to activation ratios of 39 % and nearly 100 % in the regrown and non-regrown regions, respectively. This research highlights a novel approach for evaluating site-specific activation ratios in poly-Si through the integrated use of DHEM and APT. [Display omitted] [ABSTRACT FROM AUTHOR]