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Abstract 3D neuromorphic hardware system is first demonstrated in neuromorphic application as on‐chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non‐volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware‐based neural system, considering the possibility of device degradation in both volatile and non‐volatile memory devices demonstrated by the hardware neural system.

Abstract The rapid advancement of AI‐enabled applications has resulted in an increasing need for energy‐efficient computing hardware. Logic‐in‐memory is a promising approach for processing the data stored in memory, wherein fast and efficient computations are possible owing to the parallel execution of reconfigurable logic operations. In this study, a dual‐logic‐in‐memory device, which can simultaneously perform two logic operations in four states, is demonstrated using van der Waals ferroelectric field‐effect transistors (vdW FeFETs). The proposed dual‐logic‐in‐memory device, which also acts as a two‐bit storage device, is a single bidirectional polarization‐integrated ferroelectric field‐effect transistor (BPI‐FeFET). It is fabricated by integrating an in‐plane vdW ferroelectric semiconductor SnS and an out‐of‐plane vdW ferroelectric gate dielectric material—CuInP2S6. Four reliable resistance states with excellent endurance and retention characteristics were achieved. The two‐bit storage mechanism in a BPI‐FeFET was analyzed from two perspectives: carrier density and carrier injection controls, which originated from the out‐of‐plane polarization of the gate dielectric and in‐plane polarization of the semiconductor, respectively. Unlike conventional multilevel FeFETs, the proposed BPI‐FeFET does not require additional pre‐examination or erasing steps to switch from/to an intermediate polarization, enabling direct switching between the four memory states. To utilize the fabricated BPI‐FeFET as a dual‐logic‐in‐memory device, two logical operations were selected (XOR and AND), and their parallel execution was demonstrated. Different types of logic operations could be implemented by selecting different initial states, demonstrating various types of functions required for numerous neural network operations. The flexibility and efficiency of the proposed dual‐logic‐in‐memory device appear promising in the realization of next‐generation low‐power computing systems.