Power management is becoming important aspect as the size of transistor is shrinking. For processor design, Reduced Instruction Set Computer (RISC) architecture is preferable as compared to Complex Instruction Set Computer (CISC) architecture because of its simplicity and availability. To design the low power RISC processor, there are a few techniques that had been used earlier, such as a) pipelining and b) Common Power Format language to generate power intent of RISC processor design. In the present work, for designing a 16-bit RISC processor with low power consumption, a multi-voltage design technique has been used. In this technique, different supply voltages are provided to different blocks of the design. This technique is implemented with the help of Unified Power Format (UPF). Further, various operations such as ADD, SUB, INVERT, AND, OR, Right Shift, Left Shift, and Less Than are verified on modelsim for the designed 16-bit RISC processor. [ABSTRACT FROM AUTHOR]