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This paper presents a single-inductor multiple-output (SIMO) DC-DC converter with fixed-frequency victim-last charge control. This scheme switches the load-transient channel (victim) to the last of the charging sequence, addressing the inherent cross-regulation issue in conventional charge control SIMO. We first analyze why the conventional fixed-frequency charge control has such an issue. Then, we present the working principle of the proposed scheme. After that, we propose a charge-error calibration technique that minimizes the side effects caused by victim-last control, ensuring a smooth order switching of the original last channel. We implemented and fabricated the proposed SIMO DC-DC converter in a 0.18- $\mu $ m BCD process. Measurement results show that we are able to reduce the cross-regulation to 0.057mV/mA with a 225-mA load step under fixed switching frequency. The measured peak efficiency is 84.1%.

This paper proposes a radio-frequency (RF) cross-connected (CC) rectifier with LC source degeneration (CCLC). The LC network resonates at twice of the working RF frequency, shaping the drain-source and gate-source voltages of the rectifying transistors of the CC rectifier. As a result, the proposed scheme reduces the transistors’ reverse current and the shoot-through current, and thus the root mean square current of the switches, improving the power conversion efficiency (PCE). Meanwhile, it has a better input impedance matching over a wide input power range from the voltage reshaping. Subsequently, we implement the CCLC topology in both one-stage and two-stage CC rectifiers. To reduce the silicon area, we design coupled inductors for the two LC networks of the two-stage CCLC rectifier. We fabricated the rectifiers using a 65-nm CMOS process. The measured PCE of the one-stage and two-stage rectifiers are 67.6% and 61.2%, respectively. The proposed scheme has a wider dynamic range than previous works.

This brief proposes an ultra-low-power self-biased CMOS voltage reference (SBCVR) with the drain-induced-barrier-lowering (DIBL) effect compensation to improve the line sensitivity (LS) and low-frequency power supply rejection ratio (PSRR). To reduce the dependence of bias current $(I_{\mathrm{ B}})$ on the supply voltage $(V_{\mathrm{ DD}})$ owing to the DIBL effect, the gate-source voltage $(V_{\mathrm{ GS}})$ of biasing transistor is adaptively regulated by $V_{\mathrm{ DD}}$ . In this way, the DIBL effect compensation is achieved, while the $I_{\mathrm{ B}}$ is almost immune to $V_{\mathrm{ DD}}$ . The presented SBCVR is fabricated in a 0.18- $\mu \text{m}$ CMOS process, while 18 samples have been measured. The results show that its average LS reaches 0.016%/V and has been decreased by almost 85% compared to the one without the DIBL effect compensation. The design can also achieve a PSRR of −62.5dB at 10Hz. Meanwhile, the average reference voltage $(V_{\mathrm{ REF}})$ is 317.6mV with a variation of 0.52% $\sigma /\mu $ . The average temperature coefficient (TC) is 86.6 ppm/°C without trimming from 0°C to 100°C, and the minimum power consumption at 27°C is 521pW. The area of the reported SBCVR with the DIBL effect compensation is only 0.0016mm2.

This brief proposes a nano-watt self-biased CMOS voltage reference (SBCVR) with a quasi self-cascode current mirror (QSCCM) for better line sensitivity (LS) and power supply rejection ratio (PSRR). A self-cascode MOSFET (SCM) and a cascode structure are combined as the QSCCM to reduce the variations of bias current $(I_{\mathrm{ B}})$ through the QSCCM, comparing to conventional ones. Then, the $I_{\mathrm{ B}}$ is fed into an active load to acquire a more stable reference voltage $(V_{\mathrm{ REF}})$ against the supply voltage $(V_{\mathrm{ DD}})$ without using any additional native devices, amplifiers, pre-regulation circuits, and DIBL compensation circuits. The proposed SBCVR with the QSCCM is fabricated in a standard $0.18 \mu \text{m}$ CMOS process, while 22 chip samples are measured. The results show that the average LS is 0.011%/V when the $V_{\mathrm{ DD}}$ varies from 0.8 V to 1.8 V. The average PSRR are −76dB, −53 dB, and −59 dB at 10Hz, 1kHz, and 1MHz respectively. Moreover, it can produce a $V_{\mathrm{ REF}}$ of 293 mV and consume a supply current of 1.95 nA $(V_{\mathrm{ DD}}=$ 1V) at 27 °C. The average temperature coefficient (TC) is 66.1 ppm/°C without trimming in the temperature range from −40 °C to 85 °C, while the total area is only 0.004 mm 2.

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