The development and implementation of cost-effective, reliable, low-power, and compact mmwaveand sub-THz systems could represent a significant technological advancement, potentiallycreating numerous opportunities for industrial applications. These applications include advancedradar systems, high-resolution imaging, and sensing applications in future D- and G- frequencyband systems, and they demand consistent high-power and broadband operation to enable ultrafast,low-latency communication with increased data rates. To serve this end, power amplifiers(PAs) and amplifiers play a key role in these commmunication systems. The power that a mmwavetransceiver radiates is directly impacted by the output power of its power amplifier, and hence,its improvement is essential for expanding communication range and overcoming the challenges ofpropagation losses and environmental factors. Moreover, broadband PAs can considerably improvethe power efficiency of multi-standard system-on-chips (SoCs) by eliminating the need for lossyseries switches at the outputs of the PAs for different frequency bands/standards, and effectivelyimprove the output power and power efficiency. At mm-wave frequencies, power amplificationtechniques encounter limitations due to increased parasitc loss and reduced maximum available gainfrom the device. Additionally, highly efficient PAs are essential for extending system operation andreducing thermal management issues. These requirements present significant technical challengesfor millimeter-wave PAs and amplifiers in achieving high output power, efficiency, high gain, andwideband performance simultaneously. This work aims to introduce innovative architectures andmethodologies to address these challenges.First, a new analysis and methodology on design of cascaded series-connected (Stacked) poweramplifier is introduced. Using transistor small-signal equivalent model, the proposed theory studiesthe output power, maximum efficinecy, power gain, and compression level of stacked PAs. Theproposed approach determines the optimum design point of the PA to obtain maximum efficiencyand output power. A proof-of-concept integrated PA is implemented in a 45-nm CMOS SOI process,where stacking and parallel power combining techniques are adopted to achieve 18.7dBm Pout and4.8% PAE at 200 GHz. The designed PA achieves the highest Pout and PAE amongst all the CMOScounterparts at 200 GHz.In the second part of this dissertation, the proposed stacked theory is extended and appliedto a broadband design. A wideband, low loss , balanced power combining technique consisting oftwo parallel symmetric short-circuited interdigital coupled-line sections with loaded extended-portsand a defected ground structure is introduced to realize a compact transformer with enhancedbandwidth and reduced loss. The proposed combiner network mitigates the negative impact ofinterwinding capacitance that typically occurs in conventional transformer-based power combiningmethods, and hence, has excellent phase/amplitude balance. A wideband highly-efficient 154-to-199 GHz PA prototype based on the proposed combining technique is implemented in a 45-nm SOISiGe BiCMOS process. The designed PA achieves the highest OP1dB as well as the highest PAEat OP1dB in silicon. Furthermore, the PA demonstrates very flat Psat and PAEmax, achieving1-dB BW of 45 GHz (25.7%) from 154-to-199GHz, which is the highest among the state-of-theartincluding both silicon-based and InP-based works. Furthermore, the PA supports high datarate modulated waveforms including 16-QAM (up to 32 Gb/s), 64-QAM 6Gb/s, and QPSK (up to16 GB/s), which is a record data rate for G-band PAs.In the final part of this dissertation, we present a novel feedback amplifier architecture torealize sub-terahertz, high-gain, wideband amplifiers. The pros and cons of conventional feedbackamplifier toplogies are discussed in detail and compared to that of the proposed structure. Theproposed topology employs a gain-boosting technique in each amplifier cell to increase the gainof a multistage amplifier over a broad bandwidth when cascaded with a conventional feedbackamplifier. The amplifier cell provides a close-to-Gmax gain even when passive losses are present.Two proof-of-concept G-band amplifiers were implemented in a 45-nm CMOS SOI process to verifythe feasibility of the proposed architecture. These prototypes achieve peak gains of 14 and 20.4 dBover 156–193.8 GHz and 157.4–194.2 GHz, respectively. To the best of the author’ knowledge,the presented amplifiers in this work obtain the highest bandwidth among the CMOS amplifiersoperating at near-fmax.