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Considering that Von Neumann architecture has bottlenecks in both speed and power consumption, in-memory computation is a promising solution. The in-memory computation needs to be carried out in an array composed of storage units, which can be resistive random access memory (RRAM). When using RRAMs, the data storage density can be increased by taking advantage of their multiresistive state characteristics. However, the lack of reliability is a common problem of RRAM, and it is difficult to realize high long range cyclic characteristics purely from the principle. In this work, a new 3-D device based on RRAM is proposed, which is able to realize 2-bit vector multiplication and multibit storage. Analysis and SPICE simulation are conducted to validate the feasibility. The proposed device does not need to join the write-checking process and can greatly promote the improvement of area, storage density, and operation speed, providing a new route for the future in-memory computing. Compared to traditional CMOS circuits used for vector multiplication, our proposed device can achieve 93.75% reduction in terms of number of devices.