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HfOx-based ferroelectric random access memories (FeRAMs) have been proposed as a promising candidate to further dynamic random access memory (DRAM) scaling. This article presents a bitcell design space exploration of HfZrOx-based FeRAM based on a 2T1C testbench representative of a 64-kb 1T1C subarray at 40-nm CMOS technology. We first explore the impact of ferroelectric capacitor (FeCAP) sizing on the read sensing margin (SM) and speed with eight different blocks in the subarray, supported by a hardware-calibrated FeCAP compact model. We identify the capacitance ratio ( ${C} _{\text {R}}$ ) between the bitline parasitic capacitance ( ${C} _{\text {BL}}$ ) and the FeCAP capacitance ( ${C} _{\text {FE}}$ ) as the critical design parameter for bitcell SM optimization, with a maximum ${C} _{\text {R}}$ of 41 permitted for the given FeCAP technology. Furthermore, we investigate the impact of FeCAP sizing on ferro-grain granularity (FGG)-induced variability. Our findings clarify that SM variability worsens with increasing FeCAP size but does not significantly affect the readability overall. Additionally, we examine the consequences of FeCAP sizing on disturbance effects during write operations, concluding that larger FeCAPs help mitigate write disturbances by reducing voltage transfer to half-selected (HS) cells.

This article presents a 24-V high voltage (HV) ultrasonic driver for haptic feedback, designed to drive piezoelectric micromachined ultrasonic transducers (PMUTs) using a unipolar 0.8 $\mu \text{m}$ indium–galium–zinc–oxide (IGZO) thin-film transistor technology fabricated on a polymer substrate. A new hybrid silicon/IGZO DLL architecture is proposed to overcome the IGZO technology shortcomings by leveraging the accuracy and speed capabilities of silicon technologies. The ultrasonic driver is able to drive a transducer capacitance up to 36 pF with a 3.54 bit phase resolution and a frequency of 250 kHz occupying a pitch-matched area per pixel of 800 $\times $ 800 $\mu \text{m}$ . This work shows the first fully integrated high-voltage ultrasonic driver realized in thin-film transistor technology. As the proposed hybrid architecture enables large active driver arrays at a fraction of the cost of silicon solutions, a new range of applications can be envisioned, such as large ultrasonic haptic feedback matrices.

A novel single-event effects (SEEs) in situ error detection methodology is presented for high-speed radiation-tolerant digital integrated circuits. Two circuit-level error detection flip-flops (EDFFs) are presented and compared. The flip-flops can detect both single-event transients (SETs) and single-event upsets (SEUs) while embedded in a circuit. This in situ detection allows integrated fault detection and system-level correction and provides an integrated mechanism to monitor the devices’ environment. The prototypes were implemented in a 22-nm silicon-on-insulator (SOI) technology and are experimentally verified with two-photon absorption (TPA) laser injection.

In biomedical sensor platforms, low energy consumption is of utmost importance to extend battery life. A dominant contributor in the energy budget of such platforms is the always-on recording memory. Hence, a low energy memory is required. This paper implements such a memory with aggressive voltage scaling to run the memory in the sub-threshold region during retention. Fine grained forward error correction is a key enabler for this. It allows operation of the memory beyond the point of first failure and acts similar to EDAC techniques for timing failure detection in voltage-scaled microcontrollers. The memory is embedded in a RISC-V microcontroller and fabricated in a 22nm FDSOI technology. Measurements show an always-on retention voltage down to 170mV, which results in a total average power of only 5.11uW, a 70% reduction compared to the signoff point. The memory is extensively tested with memtest and found to be fully functional up to 1.2 MHz.

Abstract: UML has been widely accepted by the software community for several years. As electronic systems design can no longer be seen as an isolated hardware design activity, UML becomes of significant interest as a unification language for systems description combining both HW and SW components. This article provides a comprehensive view of the UML applied to System-on-Chip (SoC) and hardware-related embedded systems design. The modeling concepts in the UML language are first introduced, including major diagrams for the representation of the behavior and the structure of systems. The principles behind application specific UML customizations (UML profiles) are summarized, and several examples relevant for SoC design are given, such as the SysML (System Modeling Language) and the SoC Profile. Thereafter, various approaches associating UML with existing HW/SW design languages are presented. Beyond language aspects, the article addresses the question of UML-based design flows, and shows how UML can be applied concretely to the development of electronic-based systems. The current situation about tool support constitutes the last focus of the article. In particular, we show how UML tools can be combined with well-known simulation environments, such as MATLAB.

In this work, five different logic architectures [diode-load (DL), dual-input diode-load (DINP-DL), pseudo-CMOS (P-CMOS), crossover, and differential] for digital circuits in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technologies are analyzed and compared. Dual-gate self-aligned (DGSA) lab technology is used to process n-type devices with a-IGZO channel on 6-in glass wafers and flexible substrates. Inverters, ring oscillators, and RFID-compatible 12-bit Manchester-encoded code generator circuits, using different logic architectures, are designed, processed, and characterized. Analyses of unipolar gates are performed to improve the digital design flow for realizing complex digital circuits. A detailed overview compares these logic architectures on different metrics such as robustness, power consumption, performance, and area with the aim of choosing the most optimal logic to comply with the specifications of targeted applications.