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This paper aims to increase the Unmanned Aerial Vehicle's (UAV) capacity for target tracking. First, a control model based on fuzzy logic is created, which modifies the UAV's flight attitude in response to the target's motion status and changes in the surrounding environment. Then, an edge computing-based target tracking framework is created. By deploying edge devices around the UAV, the calculation of target recognition and position prediction is transferred from the central processing unit to the edge nodes. Finally, the latest Vision Transformer model is adopted for target recognition, the image is divided into uniform blocks, and then the attention mechanism is used to capture the relationship between different blocks to realize real-time image analysis. To anticipate the position, the particle filter algorithm is used with historical data and sensor inputs to produce a high-precision estimate of the target position. The experimental results in different scenes show that the average target capture time of the algorithm based on fuzzy logic control is shortened by 20% compared with the traditional proportional-integral-derivative (PID) method, from 5.2 s of the traditional PID to 4.2 s. The average tracking error is reduced by 15%, from 0.8 m of traditional PID to 0.68 m. Meanwhile, in the case of environmental change and target motion change, this algorithm shows better robustness, and the fluctuation range of tracking error is only half of that of traditional PID. This shows that the fuzzy logic control theory is successfully applied to the UAV target tracking field, which proves the effectiveness of this method in improving the target tracking performance. [ABSTRACT FROM AUTHOR]

In this paper, we address scheduling methods for queue stabilization and appropriate power allocation techniques in downlink dense user-centric scalable cell-free multiple-input multiple-output (CF-MIMO) networks. Scheduling is performed by the central processing unit (CPU) scheduler using Lyapunov optimization for queue stabilization. In this process, the drift-plus-penalty is utilized, and the control parameter V serves as the weighting factor for the penalty term. The control parameter V is fixed to achieve queue stabilization. We introduce the dynamic V method, which adaptively selects the control parameter V considering the current queue backlog, arrival rate, and effective rate. The dynamic V method allows flexible scheduling based on traffic conditions, demonstrating its advantages over fixed V scheduling methods. In cases where UEs scheduled with dynamic V exceed the number of antennas at the access point (AP), the semi-orthogonal user selection (SUS) algorithm is employed to reschedule UEs with favorable channel conditions and orthogonality. Dynamic V shows the best queue stabilization performance across all traffic conditions. It shows a 10% degraded throughput performance compared to V = 10,000. Max-min fairness (MMF), sum SE maximization, and fractional power allocation (FPA) are widely considered power allocation methods. However, the power allocation method proposed in this paper, combining FPA and queue-based FPA, achieves up to 60% better queue stabilization performance compared to MMF. It is suitable for systems requiring low latency. [ABSTRACT FROM AUTHOR]

Currently, research on the lattice Boltzmann method mainly focuses on its numerical simulation and applications, and there is an increasing demand for large-scale simulations in practical scenarios. In response to this situation, this study successfully implemented a large-scale heterogeneous parallel algorithm for the lattice Boltzmann method using OpenMP, MPI, Pthread, and OpenCL parallel technologies on the "Dongfang" supercomputer system. The accuracy and effectiveness of this algorithm were verified through the lid-driven cavity flow simulation. The paper focused on optimizing the algorithm in four aspects: Firstly, non-blocking communication was employed to overlap communication and computation, thereby improving parallel efficiency. Secondly, high-speed shared memory was utilized to enhance memory access performance and reduce latency. Thirdly, a balanced computation between the central processing unit and the accelerator was achieved through proper task partitioning and load-balancing strategies. Lastly, memory access efficiency was improved by adjusting the memory layout. Performance testing demonstrated that the optimized algorithm exhibited improved parallel efficiency and scalability, with computational performance that is 4 times greater than before optimization and 20 times that of a 32-core CPU. [ABSTRACT FROM AUTHOR]

Orthogonal polynomials and their moments serve as pivotal elements across various fields. Discrete Krawtchouk polynomials (DKraPs) are considered a versatile family of orthogonal polynomials and are widely used in different fields such as probability theory, signal processing, digital communications, and image processing. Various recurrence algorithms have been proposed so far to address the challenge of numerical instability for large values of orders and signal sizes. The computation of DKraP coefficients was typically computed using sequential algorithms, which are computationally extensive for large order values and polynomial sizes. To this end, this paper introduces a computationally efficient solution that utilizes the parallel processing capabilities of modern central processing units (CPUs), namely the availability of multiple cores and multithreading. The proposed multi-threaded implementations for computing DKraP coefficients divide the computations into multiple independent tasks, which are executed concurrently by different threads distributed among the independent cores. This multi-threaded approach has been evaluated across a range of DKraP sizes and various values of polynomial parameters. The results show that the proposed method achieves a significant reduction in computation time. In addition, the proposed method has the added benefit of applying to larger polynomial sizes and a wider range of Krawtchouk polynomial parameters. Furthermore, an accurate and appropriate selection scheme of the recurrence algorithm is introduced. The proposed approach introduced in this paper makes the DKraP coefficient computation an attractive solution for a variety of applications. [ABSTRACT FROM AUTHOR]

CuGBasis is a free and open-source CUDA®/Python library for efficient computation of scalar, vector, and matrix quantities crucial for the post-processing of electronic structure calculations. CuGBasis integrates high-performance Graphical Processing Unit (GPU) computing with the ease and flexibility of Python programming, making it compatible with a vast ecosystem of libraries. We showcase its utility as a Python library and demonstrate its seamless interoperability with existing Python software to gain chemical insight from quantum chemistry calculations. Leveraging GPU-accelerated code, cuGBasis exhibits remarkable performance, making it highly applicable to larger systems or large databases. Our benchmarks reveal a 100-fold performance gain compared to alternative software packages, including serial/multi-threaded Central Processing Unit and GPU implementations. This paper outlines various features and computational strategies that lead to cuGBasis's enhanced performance, guiding developers of GPU-accelerated code. [ABSTRACT FROM AUTHOR]

This paper presents the parallelization of two widely used implicit numerical solvers for the solution of partial differential equations on structured meshes, namely, the ADI (Alternating-Direction Implicit) solver for tridiagonal linear systems and the SIP (Strongly Implicit Procedure) solver for the penta-diagonal systems. Both solvers were parallelized using CUDA (Computer Unified Device Architecture) Fortran on GPGPUs (General-Purpose Graphics Processing Units). The parallel ADI solver (P-ADI) is based on the Parallel Cyclic Reduction (PCR) algorithm, while the parallel SIP solver (P-SIP) uses the wave front method (WF) following a diagonal line calculation strategy. To map the solution schemes onto the hierarchical block-threads framework of the CUDA on the GPU, the P-ADI solver adopted two mapping methods, one block thread with iterations (OBM-it) and multi-block threads (MBMs), while the P-SIP solver also used two mappings, one conventional mapping using effective WF lines (WF-e) with matrix coefficients and solution variables defined on original computational mesh, and a newly proposed mapping using all WF mesh (WF-all), on which matrix coefficients and solution variables are defined. Both the P-ADI and the P-SIP have been integrated into a two-dimensional (2D) hydrodynamic model, the CCHE2D (Center of Computational Hydroscience and Engineering) model, developed by the National Center for Computational Hydroscience and Engineering at the University of Mississippi. This study for the first time compared these two parallel solvers and their efficiency using examples and applications in complex geometries, which can provide valuable guidance for future uses of these two parallel implicit solvers in computational fluids dynamics (CFD). Both parallel solvers demonstrated higher efficiency than their serial counterparts on the CPU (Central Processing Unit): 3.73~4.98 speedup ratio for flow simulations, and 2.166~3.648 speedup ratio for sediment transport simulations. In general, the P-ADI solver is faster than but not as stable as the P-SIP solver; and for the P-SIP solver, the newly developed mapping method WF-all significantly improved the conventional mapping method WF-e. [ABSTRACT FROM AUTHOR]

This paper aims to deploy the Google ChromeFlex Operating System and evaluate its efficiency. It uses a deep learning algorithm that analyzes all results from other users with the same browser type and on the same OS. This provides a meaningful evaluation of the computer unit's stressed components, including CPU, GPU, Memory, and Storage. Findings reveal that ChromeFlex OS works efficiently when the computer is connected online. Furthermore, GPU performance in ChromeFlex OS is lower in applications requiring graphics-related work like effects and videos. Using ChromeFlex OS on computer units used for daily tasks using Internet - based applications is recommended. ChromeFlex OS is a new operating system with limited compatibility, and most productivity tools compatible with old operating systems, such as Windows OS, MAC OS, and LINUX, among others, will not run in ChromeFlex OS. [ABSTRACT FROM AUTHOR]

This paper proposes a parallel algorithm exploiting heterogeneous computing and edge computing for anomaly detection (AD) in remotely sensed multispectral images. These images present high spatial resolution and are captured onboard unmanned aerial vehicles. AD is applied to identify patterns within an image that do not conform to the expected behavior. In this paper, the anomalies correspond to human-made constructions that trigger alarms related to the integrity of fluvial ecosystems. An algorithm based on extracting spatial information by using extinction profiles (EPs) and detecting anomalies by using the Reed–Xiaoli (RX) technique is proposed. The parallel algorithm presented in this paper is designed to be executed on multi-node heterogeneous computing platforms that include nodes with multi-core central processing units (CPUs) and graphics processing units (GPUs) and on a mobile embedded system consisting of a multi-core CPU and a GPU. The experiments are carried out on nodes of the FinisTerrae III supercomputer and, with the objective of analyzing its efficiency under different energy consumption scenarios, on a Jetson AGX Orin. [ABSTRACT FROM AUTHOR]

This paper presents a dynamic-phasor-based, average-value modeling method for power systems with extensive converter-tied subsystems. In the proposed approach, the overall system model is constructed using modular functions, interfacing both conventional and converter-tied resources. Model validation is performed against detailed Electro-Magnetic Transient (EMT) simulations. The analytical capabilities offered by the proposed modeling method are demonstrated on a modified IEEE 9-bus system. A Graphics Processing Unit (GPU)-based parallel computing approach for the solution of the resulting model is presented and exemplified on a modified IEEE 118-bus system, showing significant improvements in computing efficiency over EMT solvers. A co-simulation approach using a Central Processing Unit (CPU) and a GPU is also presented and exemplified using a modified version of the IEEE 118-bus system, demonstrating the model's parallelization. [ABSTRACT FROM AUTHOR]

Gaussian filtering, being a convolution with a Gaussian kernel, is a widespread technique in image analysis and computer vision applications. It is the traditional approach for noise reduction. In some cases, performing the exact convolution can be computationally expensive and time-consuming. To address this problem, approximations of the convolution are often used to achieve a balance between accuracy and computational efficiency, such as with running sums, Bell blur, Deriche approximation, etc. At the same time, modern computing devices support data parallelism (vectorization) via Single Instruction Multiple Data (SIMD) and can process integer numbers faster than floating-point approaches. In this paper, we describe several methods for approximating a Gaussian filter, implement the SIMD and quantized versions, and compare them in terms of speed and accuracy. The experiments were performed on central processing units with a x86_64 architecture using a family of SSE SIMD extensions and an ARMv8 architecture using the NEON SIMD extension. All the optimized approximations demonstrated 10–20× speedup while maintaining the accuracy in the range of 1 × 10 − 5 or higher. The fastest method is a trivial Stack blur with a relatively high error, so we recommend using the second-order Vliet–Young–Verbeek filter and quantized Bell blur and running sums as more accurate and still computationally efficient alternatives. [ABSTRACT FROM AUTHOR]

SLAM (Simultaneous Localization and Mapping), primarily relying on camera or LiDAR (Light Detection and Ranging) sensors, plays a crucial role in robotics for localization and environmental reconstruction. This paper assesses the performance of two leading methods, namely ORB-SLAM3 and SC-LeGO-LOAM, focusing on localization and mapping in both indoor and outdoor environments. The evaluation employs artificial and cost-effective datasets incorporating data from a 3D LiDAR and an RGB-D (color and depth) camera. A practical approach is introduced for calculating ground-truth trajectories and during benchmarking, reconstruction maps based on ground truth are established. To assess the performance, ATE and RPE are utilized to evaluate the accuracy of localization; standard deviation is employed to compare the stability during the localization process for different methods. While both algorithms exhibit satisfactory positioning accuracy, their performance is suboptimal in scenarios with inadequate textures. Furthermore, 3D reconstruction maps established by the two approaches are also provided for direct observation of their differences and the limitations encountered during map construction. Moreover, the research includes a comprehensive comparison of computational performance metrics, encompassing Central Processing Unit (CPU) utilization, memory usage, and an in-depth analysis. This evaluation revealed that Visual SLAM requires more CPU resources than LiDAR SLAM, primarily due to additional data storage requirements, emphasizing the impact of environmental factors on resource requirements. In conclusion, LiDAR SLAM is more suitable for the outdoors due to its comprehensive nature, while Visual SLAM excels indoors, compensating for sparse aspects in LiDAR SLAM. To facilitate further research, a technical guide was also provided for the researchers in related fields. [ABSTRACT FROM AUTHOR]

Smartphones, digital cameras, and other imaging devices generate vast amounts of high-resolution colored images daily, stored on devices equipped with multi-core central processing units or on the cloud. Safeguarding these images from potential attackers has become a pressing concern. This paper introduces a set of six innovative image ciphers designed to be stronger, faster, and more efficient. Three of these algorithms incorporate the State-Based Tent Map (SBTM) Chaotic Pseudo Random Number Generator (CPRNG), while the remaining three employ a proposed modified variant, SBTMPi. The Grayscale Image Cipher (GIC), Colored Image Cipher Single-Thread RGB (CIC1), and Colored Image Cipher Three-Thread RGB (CIC3) showcase the application of the proposed algorithms. By incorporating novel techniques in the confusion and diffusion phases, these ciphers demonstrate remarkable performance, particularly with large colored images. The study underscores the potential of SBTM-based image ciphers, contributing to the advancement of secure image encryption techniques with robust random number generation capabilities. [ABSTRACT FROM AUTHOR]

Modern power systems have several measurement devices for reliable, safe, and improved operation and control. Due to the high infiltration of inverter‐based resources, protecting modern power systems has become challenging. This paper proposes a new protection scheme based on the computation of 'discrepant impedance' using real‐time protocol services for data exchange. The sampled values of voltages and currents are transmitted to a central processing unit to implement the protection scheme. With the development of digital instrument transformers (IEC 61869‐9), the current and voltage samples are directly interfaced wired or wirelessly to the IEC 61850‐9‐2 process bus. The proposed protection scheme is validated with grid forming and grid following inverters on Consortium for Electric Reliability Technology Solutions (CERTS) microgrid network using a real‐time digital simulator. The protection scheme is independent of the type of energy sources and their control philosophy, operation modes and topology of the microgrid network. [ABSTRACT FROM AUTHOR]

Dance performance is an art form, which needs to cultivate students' dance skills, artistic accomplishment and stage performance ability. Sequential quadratic programming algorithm is an optimization algorithm that can be used to solve complex optimization problems. In this paper, Sequential Quadratic Programming (SQP) is applied to explore the training mode of dance performers in colleges to help dance performers develop the optimal training plan and program. Aiming at the problems existing in the training mode of dance performance talents in colleges, this paper put forward an optimization method based on SQP algorithm, and implemented its optimization scheme in actual colleges. In the planning of dance performance talent training mode, particle swarm optimization (PSO) is used to optimize SQP algorithm, so that it can have higher planning efficiency. This paper studied the goal and index system of the training of dance performance talents in colleges, generated a personalized training program, and further improved the scientific and practical effectiveness of the training mode. This paper investigated the current situation of dance performance talent training in several dance schools in a certain province of China. The survey data include practical curriculum planning, teachers' teaching philosophy and teaching content. Combined with SQP algorithm, the teaching and training program is optimized. After evaluation, it can be concluded that the SQP algorithm optimized by PSO shows good stability and accuracy. It can calculate the optimal solution of the cultivation scheme, and when calculating the optimal solution, the running time of the Central Processing Unit (CPU) was only 5.6 s, which can further improve the efficiency of the planning. Finally, through the satisfaction and resource utilization test, it can be found that the number of people who are very satisfied with the teaching content of the dance performance talent training program optimized by SQP increased from 38.4% to 52.4%. After optimization, the average utilization rate of teaching resources reached 88.1%. It can be concluded that SQP algorithm can provide scientific basis for dance education institutions to improve the training mode of dance talents. This can help dance education institutions better improve the training mode, and improve the overall quality and dance skills of dance students. [ABSTRACT FROM AUTHOR]

Quantization is a widespread method for reducing the inference time of neural networks on mobile Central Processing Units (CPUs). Eight-bit quantized networks demonstrate similarly high quality as full precision models and perfectly fit the hardware architecture with one-byte coefficients and thirty-two-bit dot product accumulators. Lower precision quantizations usually suffer from noticeable quality loss and require specific computational algorithms to outperform eight-bit quantization. In this paper, we propose a novel 4.6-bit quantization scheme that allows for more efficient use of CPU resources. This scheme has more quantization bins than four-bit quantization and is more accurate while preserving the computational efficiency of the later (it runs only 4% slower). Our multiplication uses a combination of 16- and 32-bit accumulators and avoids multiplication depth limitation, which the previous 4-bit multiplication algorithm had. The experiments with different convolutional neural networks on CIFAR-10 and ImageNet datasets show that 4.6-bit quantized networks are 1.5–1.6 times faster than eight-bit networks on the ARMv8 CPU. Regarding the quality, the results of the 4.6-bit quantized network are close to the mean of four-bit and eight-bit networks of the same architecture. Therefore, 4.6-bit quantization may serve as an intermediate solution between fast and inaccurate low-bit network quantizations and accurate but relatively slow eight-bit ones. [ABSTRACT FROM AUTHOR]

Artificial neural networks (ANNs), inspired by the human brain's network of neurons and synapses, enable computing machines and systems to execute cognitive tasks, thus embodying artificial intelligence (AI). Since the performance of ANNs generally improves with the expansion of the network size, and also most of the computation time is spent for matrix operations, AI computation have been performed not only using the general-purpose central processing unit (CPU) but also architectures that facilitate parallel computation, such as graphic processing units (GPUs) and custom-designed application-specific integrated circuits (ASICs). Nevertheless, the substantial energy consumption stemming from frequent data transfers between processing units and memory has remained a persistent challenge. In response, a novel approach has emerged: an in-memory computing architecture harnessing analog memory elements. This innovation promises a notable advancement in energy efficiency. The core of this analog AI hardware accelerator lies in expansive arrays of non-volatile memory devices, known as resistive processing units (RPUs). These RPUs facilitate massively parallel matrix operations, leading to significant enhancements in both performance and energy efficiency. Electrochemical random-access memory (ECRAM), leveraging ion dynamics in secondary-ion battery materials, has emerged as a promising candidate for RPUs. ECRAM achieves over 1000 memory states through precise ion movement control, prompting early-stage research into material stacks such as mobile ion species and electrolyte materials. Crucially, the analog states in ECRAMs update symmetrically with pulse number (or voltage polarity), contributing to high network performance. Recent strides in device engineering in planar and three-dimensional structures and the understanding of ECRAM operation physics have marked significant progress in a short research period. This paper aims to review ECRAM material advancements through literature surveys, offering a systematic discussion on engineering assessments for ion control and a physical understanding of array-level demonstrations. Finally, the review outlines future directions for improvements, co-optimization, and multidisciplinary collaboration in circuits, algorithms, and applications to develop energy-efficient, next-generation AI hardware systems. [ABSTRACT FROM AUTHOR]

In response to challenges in traditional offline experiments in optical physics, such as high trial-and-error costs, expensive equipment, limited design parameters, and restricted explanations of instrument structures and principles, this paper proposes a design method for an optical physics virtual simulation system based on Unreal Engine 5. The method employs a generic design architecture to partition system units and utilizes technologies like pixel streaming, rendering engines, and physics engines to implement the design of the virtual simulation system. This system covers the entire experimental process, including video learning, instrument adjustment, phenomenon observation, data measurement and recording, and grade inquiry. The proposed design method enhances the immersive experience of experiments, reduces the hardware performance requirements for users, and allows access and utilization across multiple platforms. It efficiently facilitates physics teaching through simulated experiments, thereby effectively improving the quality of experimental teaching. Finally, through a comparison with existing virtual simulation systems, it is demonstrated that the system can save approximately 94.76% of the average CPU usage and provide better immersion and user experience advantages. [ABSTRACT FROM AUTHOR]

As the basic and core component of electronic systems, CPU security is extremely important to network security. Even an unremarkable faulty instruction on the CPU may lead to serious security problems, such as the operating system crashes or privilege increase since it is often considered as a trusted black box. Therefore, CPU instruction detection is particularly crucial to CPU security. However, most existing methods of CPU instruction detection, based on the inconsistency of microarchitecture and instruction set design, suffer from slow speed and low accuracy. Our work is motivated to propose a practical framework for searching CPU undocumented instruction with fast speed and high accuracy. In this paper, we put forward a general framework InsFinder to detect undocumented instruction on CISC and RISC CPU by an efficient and accurate fuzzing method. It makes use of the instruction format to make advanced predictions, which greatly reduces the search space. Moreover, by introducing classification, de-redundancy, and verification, InsFinder greatly improves the detection accuracy. Experiments show that compared with the existing methods, InsFinder is more effective which costs at least 50% less processing time in detecting undocumented instructions on x86-64, ARM64, and RISC-V, and more accurate which divided the detection results into 4 categories. After filtering, the detection results were reduced from millions to less than 10,000. [ABSTRACT FROM AUTHOR]

Plastic waste pollution has become one of the most significant environmental concerns in recent years. The accumulation of plastic waste has been observed in various locations worldwide, leading to environmental damage and health hazards. In this paper, a system is proposed for the detection and segregation of plastic waste using a Robotic arm manipulator based on YOLOv5 and Raspberry Pi. YOLOv5 is an advanced object detection algorithm that can identify plastic waste in images. The Raspberry Pi is a low-cost, small-sized computer that can be used as the central processing unit for the proposed system. The system includes a camera module that captures images of the waste material in real time, and an ultrasonic sensor to measure distance of the object. It detects and identifies the plastic waste in the image. Then, using the 3-D coordinate values calculated from the data gathered from the camera and ultrasonic sensor, plastic waste is separated using a robotic arm by applying inverse kinematics, controlled by the Raspberry Pi. The proposed system's performance was evaluated using various custom datasets, and the results show that it can effectively detect and segregate plastic waste from other types of waste materials. [ABSTRACT FROM AUTHOR]

In recent years, the application of variable-order (VO) fractional differential equations for describing complex physical phenomena ranging from biology, hydrology, mechanics and viscoelasticity to fluid dynamics has become one of the most hot topics in the context of scientific modeling. An interesting aspect of VO operators is their capability to address the behavior of scientific and engineering systems with time and spatially varying properties. The VO fractional diffusion equation is a fundamental model that allows transitions among sub-diffusive, diffusive and superdiffusive behaviors without altering the underlying governing equations. In this paper, we considered the two-dimensional fractional diffusion equation with the Caputo time VO derivative, which is essential for describing anomalous diffusion in real-world complex systems. A new Crank-Nicolson (C-N) difference scheme and an efficient explicit decoupled group (EDG) method were proposed to solve the problem under consideration. The proposed EDG method is based on a skewed difference scheme in conjunction with a grouping procedure of the solution grid points. Special attention was devoted to investigating the stability and convergence of the proposed methods. Three numerical examples with known exact analytical solutions were provided to illustrate our considerations. The proposed methods were shown to be stable and convergent theoretically as well as numerically. In addition, a comparative study was done between the EDG method and the C-N difference scheme. It was found that the proposed methods are accurate in simulating the considered problem, while the EDG method is superior to the C-N difference method in terms of Central Processing Unit (CPU) timing, verifying the efficiency of the former method in solving the VO problem. [ABSTRACT FROM AUTHOR]

Arithmetic primitives are necessary in order to conduct computations on large numbers in arithmetic circuit implementations including multiplications, additions, subtractions, and divisions. Because of the importance of computations in the central processing unit, effective design of arithmetic circuit has been part of the most important fields of research for design engineers. In order to create low-power and energy-efficient portable processors for image and digital signal processing, as well as cryptography applications, the switching activity factor and cell count must be reduced. This research focuses on the reversible digital full adder circuit, which is a key element in establishing the Energy Delay Product (EDP) for various computer applications. Here, a new reversible binary full adder is designed using the switching activity concept and the logic decomposition method. The internal blocks for reversible full adders such as Feynman Gate, Toffoli Gate, and New Gate are designed first, then a new reversible binary full adder is developed using the proposed method. In this paper, conventional and proposed reversible full adders are synthesized using the Xilinx Vivado design suite for the Zynq-7000 family of device configuration. According to the implementation results, the proposed reversible full adder circuit consumes less dynamic power dissipation than the existing method in comparison. Furthermore, a formulae-based evaluation is conducted on the implementation results to estimate the EDP of the design. The proposed reversible full adder design can achieve a 32.3% EDP improvement compared to the Proposed Full Adder. [ABSTRACT FROM AUTHOR]

The Craig–Bampton (CB) method is a well-known substructuring technique that reduces the size of a finite element model (FEM) using a set of vibration modes. For large FEA models, the reduction process could be computationally expensive since it requires algebra operations on FEM mode shapes and FEM system sparse matrices. In this paper, we investigate the potential of usage of GPU parallel processing to speed up solving the system of linear equations that results from the CB reduction process made for a model of cyclic structures. A Python based high-level approach, employing the CuPy, GinkGo and STRUMPACK libraries on the GPU, is compared with an optimized Fortran code. In side-to-side comparisons, employing the same inputs, the Python-GPU code is run on a single GPU device and the Fortran code is run on a multi-core compute node. The CB reduction process was split into several parts, each dealing with different kind of algebraic formulation of the problem. Performance comparisons were focused on the sparse system linear solver, since it turned out to be the most time-consuming part. The results suggest that the current GPU-based linear sparse solvers do not surpass the state-of-the-art CPU-based MKL PARDISO solver (at least up to 1M DOFs). [ABSTRACT FROM AUTHOR]

All-optical arithmetic and logic unit is an integral part of contemporary optical data processing network. Accordingly, in this paper a method to develop all-optical arithmetic unit has been proposed. The proposed logic unit consists of semiconductor optical amplifier (SOA) whose fast non-linear characteristics have been utilized for the execution of numerous binary logic operations such as AND, OR, NAND, NOR, EXOR, buffer etc., as well as arithmetic operations, for instance half-addition and half-subtraction, etc. Numerical simulations for the various logic operations have been realized and output verified for the 100 Gbps data rate. Numerical executions have been also done for the crucial key parameters as the bias voltage, confinement factor, and laser power, yielded with good extinction ratio more than 10 dB. The proposed design consists of SOA with benefits of design as rapid switching speed, consumes low power and avoids optoelectronic translation. The design is having with good prospect for impending all optical complex computing networks. [ABSTRACT FROM AUTHOR]

The Internet of Everything is leading to an increasingly connected intelligent digital world. Envisaged sixth-generation wireless networks require new solutions and technologies due to stringent network requirements. The benefits of cell-free massive MIMO (CF-mMIMO) and non-orthogonal multiple access (NOMA) have brought substantial attention to these approaches as potential technologies for future networks. In CF-mMIMO, numerous distributed access points are linked to a central processing unit, which allocates the same time-frequency resources to a smaller group of users. On the other hand, NOMA can support more users than its orthogonal counterparts by utilizing non-orthogonal resource allocation. This paper provides a comprehensive review and survey of NOMA-aided CF-mMIMO (CF-mMIMO-NOMA). Specifically, we present a comprehensive review of massive MIMO, CF-mMIMO, and NOMA. We then present a state-of-the-art research review of CF-mMIMO-NOMA. Finally, we discuss the challenges and potential of combining CF-mMIMO-NOMA with other enabling technologies to enhance performance. [ABSTRACT FROM AUTHOR]

Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field-Programmable Gate Array) enables the delegating of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support the CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows encountered limitations to be overcome and the flexibility known from high-level solutions and high performance achieved with low-level programming to be maintained without the need for a high financial background. [ABSTRACT FROM AUTHOR]

Non-Orthogonal Multiple Access (NOMA) is an emerging multiple access scheme for the fifth-generation (5G) and beyond 5G mobile communications. Since NOMA supports a massive number of users simultaneously in a single time/frequency resource block through power domain multiplexing. However, the "Successive Interference Cancellation (SIC)" decoding technique at the receiver is an intricate task in the NOMA systems. Even though SIC operates in a sequential manner, multiple parallel SIC operations can be performed when deploying user pairing. Hence, outsourcing the efficient parallel processing devices is a suitable solution to compute all clusters SIC swiftly. In this paper, we design an efficient high-speed FPGA-based hardware accelerator for SIC implementation in uplink NOMA systems with user pairing on the 32-bit low-memory edge device (PYNQ-Z2 board). Ultimately, experimental results corroborate that the proposed accelerator design provides better SIC computation time than the NVIDIA Tesla K80 Graphics Processing Unit, Central Processing Unit, and ARM-Processor on PYNQ-Z2 board. [ABSTRACT FROM AUTHOR]

The finite‐difference time‐domain (FDTD) method often demands numerous grids for fine structure analysis, leading to high computational costs. To address this challenge, a subgridding scheme emerges as an attractive solution. However, the explicit nature of the FDTD subgrid method, constrained by Courant–Friedrichs–Lewy (CFL) conditions, can lead to inefficiencies with complex structures. In response, the leapfrog alternating‐direction implicit (ADI)‐FDTD method, exhibiting unconditional stability, has been developed to overcome CFL limitations. This paper presents a hybrid approach merging the one‐step leapfrog ADI‐FDTD method with a subgridding scheme using heterogeneous computing. By optimizing hardware usage and leveraging different device performances, this approach maximizes throughput in heterogeneous systems. Central processing units and graphics processing units handle workloads to minimize system latency. Simulation results on heterogeneous platforms demonstrate superior efficiency over single processor setups while maintaining simulation accuracy, especially in analyzing electromagnetic scattering from multiscale structures. [ABSTRACT FROM AUTHOR]

Two key challenges in optimal control include efficiently solving high-dimensional problems and handling optimal control problems with state-dependent running costs. In this paper, we consider a class of optimal control problems whose running costs consist of a quadratic on the control variable and a convex, non-negative, piecewise affine function on the state variable. We provide the analytical solution for this class of optimal control problems as well as a Hopf-type representation formula for the corresponding Hamilton-Jacobi partial differential equations. Finally, we propose efficient numerical algorithms based on our Hopf-type representation formula, convex optimization algorithms, and min-plus techniques. We present several high-dimensional numerical examples, which demonstrate that our algorithms overcome the curse of dimensionality. We also describe a field-programmable gate array (FPGA) implementation of our numerical solver whose latency scales linearly in the spatial dimension and that achieves approximately a 40 times speedup compared to a parallelized central processing unit (CPU) implementation. Thus, our numerical results demonstrate the promising performance boosts that FPGAs are able to achieve over CPUs. As such, our proposed methods have the potential to serve as a building block for solving more complicated high-dimensional optimal control problems in real-time. [ABSTRACT FROM AUTHOR]

Modeling and simulating the sudden depressurization of liquids inside nozzles is a significant challenge because of the plethora of the associated complex phenomena. This pressure drop together with the rapid phase change of the liquid is important characteristics of flash boiling. Computational fluid dynamics (CFD) multiscale simulations of flashing jets usually deploy additional models for modeling heat and mass transfer with long computational times. Intermediate steps such as volumetric meshing in mesh-based methods can also significantly increase the computational cost. This paper aims at providing academia and industry with a modeling tool to simulate and investigate the complex multi-facet phenomenon of flash-boiling atomization deploying a machine-learning method that could save thousand Central Processing Unit hours offering instantaneous CFD predictions. The presented machine-learning CFD method completely replaces the traditional CFD simulations workflow and requires little simulation expertise from the end-user. Notably, this is a novel model that couples for the first time the thermodynamic non-equilibrium with convolutional neural networks to simulate flashing liquid hydrogen jets thousand times faster than the standalone CFD solver. The accuracy of the novel approach is evaluated, demonstrating adequate accuracy compared to different unseen simulations and experiments. This work offers the groundwork for further accelerating CFD predictions in multiphase flow problems and could significantly improve testing flash-boiling scenarios in various industrial settings. [ABSTRACT FROM AUTHOR]

While tensor accelerated compilers have proven effective in deploying deep neural networks (DNN) on general-purpose hardware, optimizing for FPGA remains challenging due to the complex DNN architectures and the heterogeneous, semi-open compute units. This paper introduces the Automatic Kernel Generation for DNN on CPU-FPGA (AKGF) framework for efficient deployment of DNN on heterogeneous CPU-FPGA platforms. AKGF generates an intermediate representation (IR) of the DNN using TVM's Halide IR, annotates the operators of model layers in the IR to compute them on the corresponding hardware cores, and further optimizes the operator code for CPU and FPGA using ARM's function library and the polyhedral model to enhance model inference speed and power consumption. The experimental tests conducted on a CPU-FPGA board validate the effectiveness of AKGF, demonstrating significant acceleration ratios (up to 6.7x) compared to state-of-the-art accelerators while achieving a 2x power optimization. AKGF effectively leverages the computational capabilities of both CPU and FPGA for high-performance deployment of DNN on CPU-FPGA platforms. [ABSTRACT FROM AUTHOR]

Serial crystallography experiments at synchrotron and X‐ray free‐electron laser (XFEL) sources are producing crystallographic data sets of ever‐increasing volume. While these experiments have large data sets and high‐frame‐rate detectors (around 3520 frames per second), only a small percentage of the data are useful for downstream analysis. Thus, an efficient and real‐time data classification pipeline is essential to differentiate reliably between useful and non‐useful images, typically known as 'hit' and 'miss', respectively, and keep only hit images on disk for further analysis such as peak finding and indexing. While feature‐point extraction is a key component of modern approaches to image classification, existing approaches require computationally expensive patch preprocessing to handle perspective distortion. This paper proposes a pipeline to categorize the data, consisting of a real‐time feature extraction algorithm called modified and parallelized FAST (MP‐FAST), an image descriptor and a machine learning classifier. For parallelizing the primary operations of the proposed pipeline, central processing units, graphics processing units and field‐programmable gate arrays are implemented and their performances compared. Finally, MP‐FAST‐based image classification is evaluated using a multi‐layer perceptron on various data sets, including both synthetic and experimental data. This approach demonstrates superior performance compared with other feature extractors and classifiers. [ABSTRACT FROM AUTHOR]

Continuous constraint satisfaction is prevalent in many science and engineering fields. When solving continuous constraint satisfaction problems, it is more advantageous for practitioners to derive all feasible regions (i.e., the solution space) rather than a limited number of solution points, since these feasible regions facilitate design concept generation and design tradeoff evaluation. Several central processing unit (CPU)-based branch-and-prune methods and geometric approximation methods have been proposed in prior research to derive feasible regions for continuous constraint satisfaction problems. However, these methods have not been extensively adopted in practice, mainly because of their high computational expense. To overcome the computational bottleneck of extant CPU-based methods, this paper introduces a GPU-based parallel region classification method to derive feasible regions for continuous constraint satisfaction problems in a reasonable computational time. Using interval arithmetic, coupled with the computational power of GPU, this method iteratively partitions the design space into many subregions and classifies these subregions as feasible, infeasible, and indeterminate regions. To visualize these classified regions in the design space, a planar visualization approach that projects all classified regions into one figure is also proposed. The GPU-based parallel region classification method and the planar visualization approach are validated through two case studies about the bird function and the welded beam design. These case studies show that the method and the approach can solve the continuous constraint satisfaction problems and visualize the results effectively and efficiently. A four-step procedure for implementing the method and the approach in practice is also outlined. [ABSTRACT FROM AUTHOR]

Aiming at problems such as tracking failure caused by illumination changes often encountered during unmanned aerial vehicle (UAV) tracking, a target tracking algorithm with illumination adaptive and future-aware correlation filters is proposed based on the background-aware correlation filters (BACF) algorithm, which realizes reliable UAV tracking tasks at night. First, the dark scene is recognized, and an efficient image enhancement module is used to enhance the brightness of low illumination images. Then a future-aware module is constructed to train the tracking model using the contextual information of the target in the next frame for better robustness. Finally, the model updating stage involves adaptive filter updating and adaptive learning rate updating to enhance target tracking precision. The results of the comparison experiments with the state-of-the-art algorithms on the UAVDark135, UAVDT, and DTB70 datasets show that the algorithm in this paper outperforms the state-of-the-art tracking methods and has better tracking performance under light changes and fast motion (FM) scenarios. The tracking speed on a single Central processing unit (CPU) reaches 49 FPS, which satisfies the real-time requirement of UAV tracking. [ABSTRACT FROM AUTHOR]

The defect of insulators on the power line may lead to the failure of the electric transmission system, which in turn endangers the safe and reliable operation of the whole power system. Therefore, timely and accurate detection of insulators has become a current research hotspot. However, manual inspection cannot guarantee real-time detection and is prone to security accidents. Thanks to the convenience of Unmanned Aerial Vehicles (UAVs), collecting insulator images by UAVs and designing detection algorithms on insulators for real-time and accurate insulator detection have become a practical option. In this paper, considering the poor computing resources of UAVs, a lightweight object detection algorithm, NanoDet, is trained to detect insulators. In addition, to fully utilize the computing resources, the proposed model is segmented. Power-efficient layers are mapped to the central processing units (CPUs) for execution. Experimental results indicate that the proposed model can cut down the power consumption by up to 46.4% without violating the time constraint. [ABSTRACT FROM AUTHOR]

Three‐dimensional (3D) reconstruction is a pivotal research area within computer vision and photogrammetry, offering a valuable foundation of data for the development of smart cities. However, existing methods for constructing 3D models from unmanned aerial vehicle (UAV) images often suffer from slow processing speeds and low central processing unit (CPU)/graphics processing unit (GPU) utilization rates. Furthermore, the utilization of cluster‐based distributed computing for 3D modelling frequently results in inefficient resource allocation across nodes. To address these challenges, this paper presents a novel approach to 3D modelling in clusters, incorporating a dynamic load‐balancing strategy. The method divides the 3D reconstruction process into multiple stages to lay the groundwork for distributing tasks across multiple nodes efficiently. Instead of traditional traversal‐based communication, this approach employs gossip communication techniques to reduce the network overhead. To boost the modelling efficiency, a dynamic load‐balancing strategy is introduced that prevents nodes from becoming overloaded, thus optimizing resource usage during the modelling process and alleviating resource waste issues in multidevice clusters. The experimental results indicate that in small‐scale data environments, this approach improves CPU/GPU utilization by 35.8%/23.4% compared with single‐machine utilization. In large‐scale data environments for cluster‐based 3D modelling tests, this method enhances the average efficiency by 61.4% compared with traditional 3D modelling software while maintaining a comparable model accuracy. [ABSTRACT FROM AUTHOR]

Getting proper rest is an essential issue, but it is neglected as the major component of every person's overall health and well-being. Enough proper rest has a lot of proven health benefits. This paper aims at proposing a systematic framework to find the suitable pillows and mattresses for individuals to have proper rest and sleep. The proposed system includes a set of force-sensing resistors (FSR), thermal sensors, humidity-thermal sensors, and a central unit to process the acquired data. Customized software in LabVIEW is developed to monitor the results and ultimately identify the proper ergonomic mattresses and pillows for users. Initial experiments were performed based on zonal performance and multitasking to design, construct, and test each system as a novel hypothesis. The studies and tests were carried out in two steps. The first step included hardware testing and sensor arrangement, and the second step involved processing the acquired data to identify a good product. In this study, we propose a feasible framework to select convenient mattresses and pillows for each person. [ABSTRACT FROM AUTHOR]

As the extensive use of cloud computing raises questions about the security of any personal data stored there, cryptography is being used more frequently as a security tool to protect data confidentiality and privacy in the cloud environment. A hypervisor is a virtualization software used in cloud hosting to divide and allocate resources on various pieces of hardware. The choice of hypervisor can significantly impact the performance of cryptographic operations in the cloud environment. An important issue that must be carefully examined is that no hypervisor is completely superior in terms of performance; Each hypervisor should be examined to meet specific needs. The main objective of this study is to provide accurate results to compare the performance of Hyper-V and Kernel-based Virtual Machine (KVM) while implementing different cryptographic algorithms to guide cloud service providers and end users in choosing the most suitable hypervisor for their cryptographic needs. This study evaluated the efficiency of two hypervisors, Hyper-V and KVM, in implementing six cryptographic algorithms: Rivest, Shamir, Adleman (RSA), Advanced Encryption Standard (AES), Triple Data Encryption Standard (TripleDES), Carlisle Adams and Stafford Tavares (CAST-128), BLOWFISH, and TwoFish. The study's findings show that KVM outperforms Hyper-V, with 12.2% less Central Processing Unit (CPU) use and 12.95% less time overall for encryption and decryption operations with various file sizes. The study's findings emphasize how crucial it is to pick a hypervisor that is appropriate for cryptographic needs in a cloud environment, which could assist both cloud service providers and end users. Future research may focus more on how various hypervisors perform while handling cryptographic workloads. [ABSTRACT FROM AUTHOR]

The International Thermonuclear Experimental Reactor (ITER) magnetics diagnostic system will exploit high performance signal processing, network streaming and telemetry capabilities. Under this perspective, the adoption of the Multithreaded Application Real-Time Executor (MARTe2) control framework appeared as the most performing solution. To this aim, MARTe2 must be deployed over specific System-on-Module (SoM) platforms. In this paper, we focus on the porting of MARTe2 for the ARM® processor architecture, since it allows MARTe2 to run on a vast range of embedded platform. A series of further integration steps with respect to the state-of-the-art must be undertaken to deploy and run the complete solution. The paper will present the implementation and integration steps followed, giving also context about the application and motivations on the choice. As the target platform uses a quite standardized reference design, the described procedure can be adapted to a large number of System-on-Module based embedded boards. Specific platform adaptations, achieved using custom-developed components, offer another foundation for the further integration of the framework. Moreover, the ITER magnetics diagnostic system is required to run in real-time, therefore the implementation leverages the Asymmetric Multi-Processing (AMP) approach. AMP, in contrast with Symmetrical Multi-Processing (SMP), enables the central processing unit to run each core isolated from the others, without any operating system or orchestration layer in-between. Considering the strict quality assurance and continuous integration constraints required by the MARTe2 framework development process, the additional build system will be fully described. The described approach is based on the generic MARTe2 framework, ported on widespread ARM® architecture, and it could be easily repurposed for all scenarios where similar real-time signal acquisition, processing and streaming are required, thus enabling the rapid deployment of real-time control platforms with off-the-shelf components. • MARTe2 represents a standard in realtime control of complex plants, such as nuclear fusion plants. • The paper describes the steps needed to integrate MARTe2 with a real world embedded platform. • The discussion covers the relevant aspects including AMP scheme, shared memory inter-core communication and boot sequencer. • The paper aims at representing a complete porting guide of MARTe2 on ARM platforms. [ABSTRACT FROM AUTHOR]

In this paper, fully coupled particle resolved direct numerical simulations are used for heat transfer calculations. For modelling fluid velocity and temperature, the immersed boundary method (IBM) is used. Particle-particle heat transfer is modelled using well-established relations from the literature. Two-way coupling between particles and fluid is obtained using a body force that is a function of the solid volume fraction present in the fluid grid cell. Results are compared with those of spouted bed experiments to validate the simulations, and good agreement is observed. At the end of the paper, several interesting characteristics of spouted bed are obtained using simulations. The speedup of the method used for simulations was tested on multi-core CPU clusters. It is observed that the simulations scales almost linearly with the number of CPUs (tests were done up to 500 CPUs), showing the capability of the particle resolved DNS to be used on multi-CPU architectures. Distribution of particle temperatures by (a) Simulations (b) Experiments at packed bed conditions; Distribution of particle temperatures by (c) Simulations (d) Experiments at spouting condition. [Display omitted] • Heat transfer in spouted bed is modelled using particle resolved DNS. • Simulations results agree well with experiments. • The underlying physics of heat transfer in a spouted bed is studied by simulations. [ABSTRACT FROM AUTHOR]