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This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well. [ABSTRACT FROM AUTHOR]

This review is aimed at the integrated circuit design community and it explores slew-rate enhancement techniques for switched-capacitor amplifiers, with a primary focus on optimizing settling time within power constraints. Key challenges are addressed, including the selection between single-stage and two-stage amplifiers, along with the utilization of advanced circuit-level techniques for slew-rate enhancement. Presently, there exists a gap in comprehensive discussion, with reliance primarily on two Figures of Merit aimed at assessing power efficiency under specific capacitive loads. However, these metrics fail to adequately assess the performance of the existing slew-rate enhancer solutions at different values of capacitive loads. As a consequence, the designer lacks clear guidelines in practical situations. This review provides a state-of-the art mapping under a figure of merit dedicated to assess the whole settling delay, and also introduces a novel performance metric which highlights the role of the circuital architectures, regardless of external operating conditions. By offering a thorough examination, this review seeks to steer future research in switched-capacitor amplifier design, thereby facilitating informed decision-making and fostering innovation in the field. [ABSTRACT FROM AUTHOR]