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This paper describes a study of transmission control procedure for computer-to-computer and computer-computer-to-terminal communication through a public packet-switched network. Four types of basic data link are defined over a packet travel path in the network, and the functions required for the data link are discussed. A process number and its associated control method are proposed as a method of packet-interleaved communication. By applying the result of the discussion and introducing the concept of a data link and a process number, a transmission control method and a call control method between packet-switched network and computers are proposed for the packet-interleaved communication on the basis of the HDLC procedure (high-level data link control procedure).

Increasing success of computer networks performed the necessity of the packet switching machine more and more powerful. But for a widely use such a machine must be cost and throughput adaptable. High degree of reliability and easy maintenance may also be provided. As packet switching functions become more and well known, using the feature of ARPA network of Cyclades network, the emphasis is put on the way of implementing these functions on a special packet switching oriented computer structure. The designed structure, as a packet switching node, handles packets working on bit sequences. The functions are decentralized over a multi-processor structure in order to increase the parallel processing. Data link procedure management is performed by two processors, the receive and send processors, who act for only one link. There are as many couples of these processors as links. To each link a switching processor is assigned performing the switching function. A packet oriented memory is provided which allows simultaneous accesses for all the receive and send processors. A core processor manages the communications between the receive, send and switch processors, the processor also deals with memory allocation, sending packet who have not been acknowledged and links failures. Furthermore a software system implemented on a micro-processor processes background functions principaly flow control function and routing table management. For that structure correctness and recovery capabilities are provided using peculiar features concerning either internal packet manipulation, or duplicated modules. As a result the cost-performance ratio is acceptable and the modularity allows to fit the node configuration to the requirements of a large scale of packet switching networks, having different characteristics related to the number of links connected to each node and to the transmission data rates on these links.

This concise paper presents a new network approach to delay minimization in a synchronous network. The delay minimization is achieved by controlling the demultiplexing frame with respect to the incoming frame in a master frame system.

The hypothesis of independent processing channels was tested in a letter-recognition task. Letter space and retinal position were varied for both unilateral and bilateral presentations of two-letter configurations. The response latencies indicated contour interference effects for small letter spaces as well as a different type of processing delay which increased rapidly with increased letter distance from the fixation point. The latter effect was assumed to represent an interaction between the feature extraction processes of the adjacent letters. Since the processing capacity decreases as a function of the distance from the fovea, the reaction times were correspondingly lengthened.

A new packet-switching network technique is described which, while utilizing certain aspects of the ARPANET technology, introduces a substantially different technique for handling traffic which is longer than a single packet in length. The technique is keyed to a common-user network environment, where a wide variety of subscriber types, ranging from computers to simple terminals, are to be serviced. Subscribers in most cases would be remotely located from the network switching nodes. By splitting the buffering between the originating and destination nodes and by essentially eliminating the segment reassembly process, substantial reductions in on-line buffering can be achieved, while still maintaining short response times for interactive messages and large bandwidths for long data exchanges. In this paper we describe the network operational concepts and traffic flow for various subscriber types, show specific examples and timing diagrams for message flows, and present a comparative analysis of the buffer sizing, throughput, and delay for this new technique compared to the well-known ARPANET technique of packet switching.

When messages are transmitted as a series of possibly noncontiguous packets, an effective priority is introduced which favors short messages. The strength of this effect upon transmission time is investigated and compared with schemes where an additional priority scheme is imposed. It is found that imposing a real priority structure can markedly influence delays when: first, the trunks are relatively heavily loaded, and second, the nodes' incoming traffic arrives over high-speed channels.

The degradation in correlation receiver performance due to signal distortion at the transmitting antenna is computed as a function of processing delay for simple but representative models of the Sanguine antenna and input waveforms. The optimum delay and minimum distortion loss are given parametrically in terms of the ratio of the 3 dB bandwidth of the signal process to that of the antenna. For the more realistic model considered the degradation can be reduced significantly to just a fraction of a dB by optimizing the receiver delay.

Any communication network has a finite traffic capacity and if it is offered traffic beyond the limit it must reject some of it. The data-communication network studied here is one employing packet switching, like the Advanced Research Project Agency (ARPA) network. It handles blocks of data, called packets, and longer messages are subdivided, rather in the same way that store in a computer is allocated in pages. A method of controlling congestion is proposed in which there is a finite number of packet carriers in the whole network. When a packet of data is delivered to its destination node the "empty" packet is available for reuse. The empties move randomly round the network and new data must capture an empty packet carrier before being launched into the network. Various elaborations are described that avoid delay in normal conditions. This so-called "isarithmic" method of congestion control supplements and does not replace end-to-end flow control.

A device for rectilinear and transverse-section scanning of the brain using 99m Tc pertechnetate is presented. The scanner has four detectors to view four different aspects of the brain simultaneously. A self-contained computer controls display and all automatic operations with no processing delay. This system permits more thorough studies with multiple rectilinear and transverse section views without moving the patient, precise orientation of views to each other and to the patient's position, minimal technician operations to assure simplicity and reliability, maximum physician operation to assure a complete examination, efficient transfer of information, and economy of design to encourage wide application.

Requirements on circuit performance in high data-rate systems depend on the type of system in which the circuits are to be used. The requirements must be derived accordingly. For the type of system in which processing delay is not a limiting factor, a theoretical analysis has disclosed two basic circuit requirements: 1) minimum time dispersion in binary elements, 2) minimum time to set a flip-flop. This paper presents the salient points of the theoretical analysis and describes circuits which uniquely meet the two basic circuit requirements. Time dispersion is minimized by applying a rapidtransfer principle to current-switching requantizing circuits. These circuits completely requantize the binary elements in both time and amplitude. The time required to store a binary element in a current-switching flip-flop is reduced by operating the transistors in the active region exclusively. Serial data rates up to 250 megabits per second have been obtained using the rapid-transfer circuit in a small test system.

In a synchronous circuit an operation is complete when a given number of clock times have elapsed since it was begun. In an asynchronous network no such indication is available, and we must either rely on the network to inform us of completion, or wait for the worst-case delay. The second method is undesirable because normally the network will complete its operation long before the worst-case delay time has elasped. It will be shown here that, for a large class of iterative circuits, the network can be designed to inform us of completion. Moreover, this can be done without recourse to monitoring all lateral states (to see when none are changing).

This paper concerns a multichannel magnetic tape recorder/reproducer whose primary function is to provide stable, real-time multiplication (100 times) of all frequencies present at the input. This is accomplished by the use of rotating playback head assembly, located near and "downstream" of a conventional record station. This arrangement yields a short processing delay and, because of the iterative scans, makes possible time division multiplexing of other system components. System requirements and characteristics are presented along with a discussion of the major engineering problems that had to be solved.

A model is developed to estimate the passage time of a block of data through a group of tandem buffered switches of a buffered data network. In particular, the first two moments and the distribution function of this block passage time are estimated. This estimation procedure contains many assumptions and heuristic arguments that are based on the author's intuition and/or experience. Simulation results of the block passage time through a sample buffered network are presented and are compared with the results of the estimation procedure. The delay performance of this example buffered network is also studied by making a delay comparison between the sample buffered network and a point-to-point private-line arrangement.

Packet broadcasting is a technique whereby data is sent from one node in a net to another by attaching address information to the data to form a packet---typically from 30 to 1000 bits in length. The packet is then broadcast over a communication channel which is shared by a large number of nodes in the net; as the packet is received by these nodes the address is scanned and the packet is accepted by the proper addressee (or addressees) and ignored by the others. The physical communication channel employed by a packet broadcasting net can be a ground based radio channel, a satellite transponder or a cable.

This paper describes a study of transmission control procedure for computer to computer and computer to terminal communication through a public packet switched network.Four types of basic data link are defined over a packet travel path in the network, and the functions required for the data link are discussed.By applying the result of the discussion and introducing the concept of a process number, a transmission control method and call control signalling method between computer and packet switched network are proposed for the packet interleaved communication on the basis of the HDLC procedure.

Electronic communications technology has developed historically almost completely within what might be called the circuit switching domain. Not until the last decade has the other basic mode of communication, packet switching, become competitive. Thus, as a technology, packet communication has only begun to be explored. Circuit switching can be defined in the broad sense as the technique of establishing a complete path between two parties for as long as they wish to communicate, whereas packet switching is where the communication is broken up into small messages or packets, attaching to each packet of information its source and destination and sending each of these packets off independently and asynchronously to find its way to the destination. In circuit switching all conflicts and allocations of resources must be made before the circuit can be established thereby permitting the traffic to flow with no conflicts. In packet switching there is no dedication of resources and conflict resolution occurs during the actual flow perhaps resulting in somewhat uneven delays being encountered by the traffic. Clearly, without the speed and capability of modern computers, circuit switching represented a cheaper and more effective way to handle communications. For radio frequency assignment and telephone exchanges the resource allocation decisions could be made infrequently enough that manual techniques were originally sufficient. Also, since voice was the main information being communicated, the traffic statistics were sufficiently compatible with this approach to make it quite economic for the period. Packet switching of a kind, the telegram, persisted throughout this period but due to the high cost of switching and the limited demand for fast message traffic never attracted much attention.

Packet multiplexing or switching systems split incoming customer messages into fixed length packets. Within a packet switching system information is transferred packet by packet. In this paper a model for a packet switching node is investigated. Terminals are connected to the node by local loops. In the model incoming messages are quantized into packets and completed packets are transferred to the desired outgoing trunk. Buffering techniques are applied to obtain high trunk utilization. In the model each trunk has a dedicated buffer which stores packets queueing up for transmission. First the statistics of packet arrival at a trunk buffer is analyzed by investigating the process of quantizing messages which arrive dispersed and overlapping in time. Then buffer requirements and overflow probabilities are derived as a function of local loop and trunk speeds and for various packet sizes.

Optimal transversal equalization is considered for a noiseless multipath channel comprising a main signal followed by a larger magnitude ghost. It is shown that for the optimal transversal equalizer, the output residual intersymbol variance decreases with increase of processing delay. For the same processing delay, the optimal transversal equalizer intersymbol variance is always larger than that of the finite optimal Wiener equalizer, especially as the magnitudes of the main signal and ghost approach equality.

An analytical formulation for determining the optimum packet size is presented. The mathematical model developed takes into consideration the message statistics, acknowledgment delays, channel-error characteristics, delays due to retransmission, packet header and the overheads due to blank padding of last packet etc. Network operational overheads have been considered to be functions of packet size. The system analysed is a half-duplex network operating in a stop-and-wait strategy for error detection and correction. The theoretical formulations lead to a 3rd-order algebraic equation having one and only one positive real root - which signifies the optimum packet size. Furthermore, these studies indicate that a packet size can be determined that minimises the network operational overheads; while the overheads due to blank padding increase more or less linearly with packet size.

In packet-switched data networks, overheads are incurred primarily due to two aspects: the protocol, i.e. headers. acknowledgements etc. and blank padding of the partially used packet. In the letter, the overhead factors due to these two sources are derived under certain assumptions. Simulations using exponentially distributed messages have been carried out, and results from these are also presented. It is shown that, under certain conditions, it is possible to have a packet size that minimises the total overheads.

Data communication is a vital part of any industrialised society, and much effort goes into optimising the use of the available resources. One way is to let the customer lease only the transmission channel and provide his own switching. A development of packet switching is discussed in this article.

A processor-controlled packet-store-and-forward data-communication system is described and performance figures are presented. The philosophy of the system is characterised by the use of a route-search packet to establish the availability of both a route through the network and the destination terminal before the message data is accepted by the network. Subsequent message-data packets are constrained to follow the path established by the route search and are maintained in correct sequence by a comprehensive acknowledgment-and-signalling procedure. This also provides the facility of error correction by retransmission, and is the basis of a convenient method for the control of buffer storage within the network. The exchange implementation comprises a control computer operating in conjunction with link terminal units that are dedicated to the control of the input and output links of the exchange and to packet assembly and checking functions. Each of these units consists of a small autonomous microcomputer module controlled by a changeable microprogram. They can thus be readily adapted to accommodate the characteristics of the particular links and error-control facilities employed.