93 results on '"PARALLEL processing"'
Search Results
2. A Comparison of List Schedules for Parallel Processing Systems.
- Author
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Adam, Thomas L., Chandy, K. M., and Dickson, J. R.
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PARALLEL processing , *ELECTRONIC data processing , *DYNAMIC programming , *RANDOM variables , *MULTIVARIATE analysis , *LINEAR programming - Abstract
The problem of scheduling two or more processors to minimize the execution time of a program which consists of a set of partially ordered tasks is studied. Cases where task execution times are deterministic and others in which execution times are random variables are analyzed. It is shown that different algorithms suggested in the literature vary significantly in execution time and that the B-schedule of Coffman and Graham is near-optimal. A dynamic programming solution for the case in which execution times are random variables is presented. [ABSTRACT FROM AUTHOR]
- Published
- 1974
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3. Algorithm 447 Efficient Algorithms for Graph Manipulation [H].
- Author
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Hopcroft, John and Tarjan, Robert
- Subjects
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ALGORITHMS , *VERTEX operator algebras , *RANDOM access memory , *CELLULAR automata , *PARALLEL processing , *COMPUTER storage devices - Abstract
Efficient algorithms are presented for partitioning a graph into connected components, biconnected components and simple paths. The algorithm for partitioning of a graph into simple paths is iterative and each iteration produces a new path between two vertices already on paths. (The start vertex can be specified dynamically.) If V is the number of vertices and E is the number of edges, each algorithm requires time and space proportional to max (V, E) when executed on a random access computer. [ABSTRACT FROM AUTHOR]
- Published
- 1973
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4. Cellular Arrays for the Solution of Graph Problems.
- Author
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Levitt, K. N., Kautz, W. H., and Ashenhurst, R. L.
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GRAPH theory , *PARALLEL processing , *COMPUTER algorithms , *ELECTRONIC data processing , *MATRICES (Mathematics) , *COMPUTER science - Abstract
A cellular array is a two-dimensional, checkerboard type interconnection of identical modules (or cells), where each cell contains a few hits of memory and a small amount of combinational logic, and communicates mainly with its immediate neighbors In the array. The chief computational advantage offered by cellular arrays is the improvement in speed achieved by virtue of the possibilities for parallel processing. In this paper it is shown that cellular arrays are inherently well suited for the solution of many graph problems. For example, the adjacency matrix of a graph is easily mapped onto an array; each matrix element is stored in one cell of the array, and typical row and column operations are readily implemented by simple cell logic. A major challenge in the effective use of cellular arrays for the solution of graph problems is the determination of algorithms that exploit the possibilities for parallelism, especially for problems whose solutions appear to be inherently serial. In particular, several parallelized algorithms are presented for the solution of certain spanning tree, distance, and path problems, with direct applications to wire routing, PERT chart analysis, and the analysis of many types of networks. These algorithms exhibit a computation time that in many cases grows at a rate not exceeding log2, n, where n is the number of nodes in the graph. Straight. forward cellular implementations of the well-known serial algorithms for these problems require about n steps, and noncellular implementations require from n2 to n3 steps. [ABSTRACT FROM AUTHOR]
- Published
- 1972
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5. Interference Between Communicating Parallel Processes.
- Author
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Gilbert, Philip, Chandler, W. J., and Randell, B.
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PARALLEL processing , *ELECTRONIC data processing , *COMPUTER programming , *COMPUTER operating systems , *SUPERCOMPUTERS , *COMPUTER science - Abstract
Various kinds of interference between communicating parallel processes have been examined by Dijkstra, Knuth and others. Solutions have been given for the mutual exclusion problem and associated subproblems, in the form of parallel programs, and informal proofs of correctness have been given for these solutions. In this paper a system of parallel processes is regarded as a machine which proceeds from one state S (i.e. a collection of pertinent data values and process configurations) to a next state 5' in accordance with a transition rule S ⇒ S . A set of such rules yields sequences of states, which dictate the system's behavior. The mutual exclusion problem and the associated subproblems are formulated as questions of inclusion between sets of states, or of the existence of certain sequences. A mechanical proof procedure is shown, which will either verify (prove the correctness of) or discredit (prove the incorrectness of) an attempted solution, with respect to any of the interference properties. It is shown how to calculate transition rules from the "partial rules" by which the individual processes operate. The formation of partial rules and the calculation of transition rules are both applicable to hardware processes as well as to software processes, and symmetry between processes is not required. [ABSTRACT FROM AUTHOR]
- Published
- 1972
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6. On Shrinking Binary Picture Patterns.
- Author
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Levialdi, S. and Newman, W.
- Subjects
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PARALLEL processing , *ARTIFICIAL neural networks , *ALGORITHMS , *COMPUTER networks , *ARTIFICIAL intelligence , *ELECTRONIC data processing - Abstract
A parallel processing algorithm for shrinking binary patterns to obtain single isolated elements, one for each pattern, is presented. This procedure may be used for counting patterns on a matrix, and a hardware implementation of the algorithm using large scale integrated technology is envisioned. The principal features of this method are the very small window employed (two-by-two elements), the parallel nature of the process, and the possibility of shrinking any pattern, regardless of the complexity of its configuration. Problems regarding merging and disconnection of patterns during the process as well as the determination of the maximum number of steps necessary to obtain a single isolated element from a pattern, are reviewed and discussed. An analogy with a neural network description, in terms of McCulloch-Pitts "neurons" is presented. [ABSTRACT FROM AUTHOR]
- Published
- 1972
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7. Subexpression Ordering in the Execution of Arithmetic Expressions.
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Ramamoorthy, C.V. and Gonzales, M.J.
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PARALLEL processing , *CACHE memory , *MULTIPROCESSORS , *BUFFER storage (Computer science) - Abstract
Presents a subexpression ordering in the execution of arithmetic expressions. Evaluation of subexpressions in serials, parallel or a combination of these modes; Minimization of expression execution time; Execution of subexpressions in order of decreasing memory and processor time requirements which is valid for configurations from a uniprocessor with an unbuffered main memory to a multiprocessor with cache buffer memory.
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- 1971
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8. On the Optimal Detection of Curves in Noisy Pictures.
- Author
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Montanari, Ugo
- Subjects
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IMAGE processing , *PARALLEL processing - Abstract
Examines a technique for recognizing systems of lines in image processing. Decision process used to recognize the input picture of the optimal system of lines; Relationship between the structure of the figure of merit and the complexity of the optimization process; Suitability of the technique for parallel processing.
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- 1971
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9. An Interrupt Based Organization for Management Information Systems.
- Author
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Morgan, Howard Lee
- Subjects
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INFORMATION resources management , *INTERRUPTS (Computer systems) , *SWITCHING circuits , *COMPUTER programmers , *CODING theory , *DATA compression - Abstract
A programming structure, language constructs, and a supervisory system organization are proposed for the design and coding of large shared data base systems. The bases for this organization are a generalized interrupt structure and the newly introduced concept of "file tagging," which is the process of associating program structures and Interrupt generating conditions with items in the data base. An algorithm for resolving conflicts which arise in scheduling the Interrupt processing routines is presented. DPL, a programming language and supervisory system in which these concepts are implemented, is used to illustrate the new organization which is proposed for management information systems. [ABSTRACT FROM AUTHOR]
- Published
- 1970
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10. Process Management and Resource Sharing in the Multiaccess System ESOPE.
- Author
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Bétourné, C., Boulenger, J., Ferrié, J., Kaiser, C., Krakowiak, S., Mossière, J., and Randell, B.
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PARALLEL processing , *ELECTRONIC data processing , *SUPERCOMPUTERS , *MULTIPROCESSORS , *PARALLEL programming , *COMPUTER operating systems - Abstract
The main design principles of the multiaccess system ESOPE are described. Emphasis is placed on basic ideas underlying the design rather than on implementation details. The main features of the system include the ability given to any user to schedule his awn parallel processes using system primitive operations, the file-memory relationship, and the allocation-scheduling policy; which dynamically takes into account recent Information about user behavior. [ABSTRACT FROM AUTHOR]
- Published
- 1970
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11. A Case Study in Programming for Parallel-Processors.
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Ashenurst, R. L. and Rosenfeld, Jack L.
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PARALLEL processing , *ELECTRONIC data processing , *COMPUTER systems , *COMPUTER programming , *INFORMATION retrieval , *COMPUTER algorithms - Abstract
An affirmative partial answer is provided to the question of whether it is possible to program parallel-processor computing systems to efficiently decrease execution time for useful problems. Parallel-processor systems ore multiprocessor systems in which several of the processors con simultaneously execute separate tasks of o single job, thus cooperating to decrease the solution time of a computational problem. The processors have independent instruction counters, meaning that each processor executes its own task program relatively independently of the other processors. Communication between cooperating processors is by means of data in storage shared by oil processors. A program for the determination of the distribution of current in an electrical network was written for a parallel-processor computing system, and execution of this program was simulated. The data gathered from simulation runs demonstrate the efficient solution of this problem, typical of a large class of important problems. It is shown that, with proper programming, solution time when Np processors are applied approaches 1/Np times the solution time for a single processor, while improper programming con actually lead to an increase of solution time with the number of processors. Storage interference and other measures of performance are discussed. Stability of the method of solution was also investigated. [ABSTRACT FROM AUTHOR]
- Published
- 1969
12. On Simulating Networks of Parallel Processes in Which Simultaneous Events May Occur.
- Author
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Parnas, David L.
- Subjects
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PARALLEL processing , *SUPERCOMPUTERS , *COMPUTER systems , *COMPUTER industry , *ELECTRONIC systems , *SIMULATION methods & models - Abstract
Some of the problems of simulating discrete event systems, particularly computer systems, on a conventional digital computer are dealt with. The systems are assumed to be described as a network of interconnected sequential processes. Briefly reviewed are the common techniques used to handle such simulations when simultaneous events do not occur, can be ignored, or can be handled by simple priority rules. Following this, the problem of dealing with simultaneous events in separate processes is introduced. An abstraction of this problem is developed which admits solution for a majority of commonly encountered problems. The technique will either find a method of simulating the parallel events or report that none can be found. In some of the latter cases it is shown to be possible to find a solution by extending the information available to the solution technique, but in many cases the technique becomes computationally unfeasible when the additional information is provided. [ABSTRACT FROM AUTHOR]
- Published
- 1969
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13. The Structure of the "THE"-Multiprogramming System.
- Author
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Dijkstra, Edsger W.
- Subjects
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MULTIPROGRAMMING (Electronic computers) , *COMPUTER systems , *MULTIPROCESSORS , *INFORMATION technology , *PARALLEL processing , *COMPUTERS - Abstract
A multiprogramming system is described in which all activities are divided over a number of sequential processes. These sequential processes are placed at various hierarchical levels, in each of which one or more independent abstractions have been implemented. The hierarchical structure proved to be vital for the verification of the logical soundness of the design and the correctness of its implementation. [ABSTRACT FROM AUTHOR]
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- 1968
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14. A Scheduling Philosophy for Multiprocessing Systems.
- Author
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Lampson, Butler W.
- Subjects
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MULTIPROCESSORS , *MULTIPROGRAMMING (Electronic computers) , *COMPUTERS , *INFORMATION technology , *ELECTRONIC data processing , *PARALLEL processing - Abstract
A collection of basic ideas is presented, which have been evolved by various workers over the past four years to provide a suitable framework for the design and analysis of multiprocessing systems. The notions of process and state vector are discussed, and the nature of basic operations on processes is considered. Some of the connections between processes and protection are analyzed. A very general approach to priority-oriented scheduling is described, and its relationship to conventional interrupt systems is explained. Some aspects of time-oriented scheduling are considered. The implementation of the scheduling mechanism is analyzed in detail and the feasibility of embodying it in hardware established. Finally, several methods for interlocking the execution of independent processes are presented and compared. [ABSTRACT FROM AUTHOR]
- Published
- 1968
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15. Three Criteria for Designing Computing Systems to Facilitate Debugging.
- Author
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van Horn, Earl C.
- Subjects
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DEBUGGING , *COMPUTER systems , *ELECTRONIC data processing , *ELECTRONIC systems , *PROGRAMMING languages , *PARALLEL programming - Abstract
The designer of a computing system should adopt explicit criteria for accepting or rejecting proposed system features. Three possible criteria af this kind are input recordability, input specifiability, and asynchronous reproducibility of output. These criteria imply that a user can, if he desires, either know or control all the influences affecting the content and extent of his computer's output. To define the scope of the criteria, the notion of an abstract machine of a programming language and the notion of a virtual computer are explained. Examples of applications of the criteria concern the reading of a time-of-day clock, the synchronization of parallel processes, protection in multipragrammed systems, and the assignment of capability indexes. [ABSTRACT FROM AUTHOR]
- Published
- 1968
- Full Text
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16. One-Pass Compilation of Arithmetic Expressions for a Parallel Processor.
- Author
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Stone, Harold S.
- Subjects
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PARALLEL processing , *COMPUTER arithmetic & logic units , *COMPILERS (Computer programs) , *ARITHMETIC , *ALGORITHMS , *COMPUTER circuits - Abstract
Under the assumption that a processor may have a multiplicity of arithmetic units, a compiler for such a processor should produce object code to take advantage of possible parallelism of operation. Most of the presently known compilation techniques are inadequate for such a processor because they produce expression structures that must be evaluated serially. A technique is presented here for compiling arithmetic expressions into structures that can be evaluated with a high degree of parallelism. The algorithm is a variant of the so-called "top-down" analysis technique, and requires only one pass of the input text. [ABSTRACT FROM AUTHOR]
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- 1967
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17. Letters to the Editor.
- Author
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Sprague, V. G., Pollack, Solomon L., Wirth, Niklaus, Knuth, Donald E., Thomas, Jr., Richard F., Henrici, Peter, Davids, Norman, and Pershing, Michael L.
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LETTERS to the editor , *COMPUTER software , *PARALLEL processing , *ELECTRONIC data processing , *COMPUTER programming - Abstract
Presents several letters to the editor referencing articles and topics discussed in previous issues. Response to "Conversion of Limited-Entry Decision Table to Computer Programs," by Solomon L. Pollack; Comments on an article related to program structures for parallel processing by J.P. Anderson; Insights on "Solution of a Problem in Concurrent Programming Control."
- Published
- 1966
18. Program Structures for Parallel Processing.
- Author
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Cheatham, Jr., T. E. and Anderson, James P.
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ALGOL (Computer program language) , *COMPUTER programming , *PARALLEL computers , *PARALLEL processing , *C (Computer program language) , *MULTIPROCESSORS - Abstract
Constructs for organizing and explicating parallel program segments are discussed as extensions to ALGOL 60. The constructs serve as meta-commands and are motivated by equipment having multiprocessing capability. [ABSTRACT FROM AUTHOR]
- Published
- 1965
19. SIMULTANEOUS PROCESSING OF JOBS ON AN ELECTRONIC COMPUTER.
- Author
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McKenney, James L.
- Subjects
MULTIMEDIA systems ,COMPUTER integrated manufacturing systems ,MANUFACTURING processes ,ELECTRONIC systems ,COMPUTER systems ,PARALLEL processing ,QUEUING theory ,PILOT (Computer program language) ,COMPUTER programming ,COMPUTER software - Abstract
The article discusses the implications of processing multiple jobs simultaneously in the same computer program. According to the author, by creating programs that can be automatically combined and segmented, a queue of work can be created for the available operating components of a computer. The author uses for an example the United States National Bureau of Standards' computer system PILOT, which consists of three computers functioning simultaneously and somewhat independently on different parts of the same program to complete the same job.
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- 1962
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20. Synchronizing Processors with Memory-Content-Generated Interrupts.
- Author
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Hill, J. Carver and Bell, G.
- Subjects
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COMPUTER systems , *ELECTRONIC systems , *INTERRUPTS (Computer systems) , *SWITCHING circuits , *SYSTEMS software , *ARRAY processors - Abstract
Implementations of the "Lock-Unlock" method of synchronizing processors in a multiprocessor system usually require uninterruptable, memory-pause type instructions. An interlock scheme called read-interlock, which does not require memory-pause instructions, has been developed for a dual DEC PDP-10 system with real-time requirements. The read-interlock method does require a special "read-interlock" instruction in the repertoire of the processors and a special "read-interlock" cycle in the repertoire of the memory modules. When a processor examines a "lock" (a memory location) with a read-interlock instruction, it will be interrupted if the lock was already set; examining a lock immediately sets it if it was riot already set (this event sequence is a read-interlock cycle). Writing into a lock clears it. Having the processor interrupted upon encountering a set lock instead of branching is advantageous if the branch would have resulted in an effective interrupt. [ABSTRACT FROM AUTHOR]
- Published
- 1973
- Full Text
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21. Interrupt Driven Programming.
- Author
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Zelkowitz, Marvin
- Subjects
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INTERRUPTS (Computer systems) , *SYSTEMS software , *SWITCHING circuits , *ELECTRONIC file management , *ELECTRONIC data processing , *SUBROUTINES (Computer programs) , *COMPUTER storage devices - Abstract
The article focuses on the work of researcher H.L. Morgan related to a new form of interrupt which he proposes to use to control the execution of a program, in his case a file management system called data processing language. Simply stated, he has attached to every subroutine a Boolean expression which, if true, would cause that subroutine to be executed. Since his implementation is via software, a relatively time-consuming check must be made whenever some condition in the program changes. The implementation is described in terms of an IBM 360 environment, but is certainly not limited to it. Essentially the implementation involves the addition of a small associate memory to the CPU which is 12N bytes long. Each entry is 12 bytes wide, and the number of entries is up to the designer of the computer. The utility of this small associative memory is shown under a wide selection of applications. It is by no means definitive in its description. Its only goal is to show the desirability of implementing such a check at the hardware level.
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- 1971
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22. Procedure-Oriented Language Statements to Facilitate Parallel Processing.
- Author
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Opler, Ascher
- Subjects
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COMPUTER software , *PROGRAMMING languages , *PARALLEL processing - Abstract
Suggests two statements which allow a programmer writing in a procedure-oriented language to indicate sections of program which are to be executed in parallel. Establishment of a range of parallel operation; Definition of two or more parallel paths within this range.
- Published
- 1965
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23. Analysis of global pattern features
- Author
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D. J. H. Moore and D Parker
- Subjects
business.industry ,Feature extraction ,Pattern recognition ,Parallel ,Artificial Intelligence ,Histogram ,Signal Processing ,Visual patterns ,Chord (music) ,Entropy (information theory) ,Computer Vision and Pattern Recognition ,Artificial intelligence ,business ,Software ,Character recognition ,Mathematics ,Parallel processing - Abstract
A fundamental method for analysing the global features of visual patterns is presented. Pattern features are considered to be synonomous with non-random distributions in the pattern statistics. In particular, the statistics of the chords of the patterns are considered, leading to the histograms of the chord lengths and angles. Peaks in these histograms indicate the presence of structure in the pattern. It is demonstrated how the points of the pattern contributing to this structure can be enhanced and/or extracted. It is argued that this is a more fundamental way of obtaining pattern features than other ad hoc methods. The chord space approach allows analytic solutions to be easily obtained for idealized patterns such as circles, parallel lines, etc. A method for implementing the algorithms on a parallel processor is indicated.
- Published
- 1974
24. Matrix Inversion Using Parallel Processing
- Author
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Marshall C. Pease
- Subjects
Artificial Intelligence ,Hardware and Architecture ,Control and Systems Engineering ,Computer science ,Gauss ,Euclidean geometry ,Linear algebra ,Inversion (meteorology) ,Algorithm ,Software ,Information Systems ,Parallel processing - Abstract
Two general methods of matrix inversion, Gauss's algorithm and the method of bordering, are analyzed from the viewpoint of their adaptability for parallel computation. The analysis is not based on any specific type of parallel processor; its purpose is rather to see if parallel capabilities could be used effectively in matrix inversion. It is shown that both methods are indeed able to make effective use of parallel capability. With reasonable assumptions on the parallelism that is available, the speeds of the two methods are roughly comparable. The two methods, however, make use of different kinds of parallelism. To implement Gauss's algorithm we would like to have (a) parallel transfer capability for n numbers, if the matrix is n X n , (b) the capability for parallel multiplication of the accessed numbers by a common multiplier, and (c) parallel additive read-in capability. For the method of bordering, we need, primarily, the capability of forming the Euclidean inner product of two n -dimensional real vectors. The latter seems somewhat harder to implement, but, because it is an operation that is fundamental to linear algebra in general, it is one that might be made available for other purposes. If so, then the method of bordering becomes of interest.
- Published
- 1967
25. Semiannual Technical Report, 1 Oct 1973-31 Mar 1974
- Abstract
This is a progress report on ARPA contract DAHC04-72-C-0001, entitled, 'ILLIAC 4 Applications Research at the Center for Advanced Computation, University of Illinois at Urbana-Champaign.' During this period there was research in the following areas: (1) Applied mathematics, (2) Pictorial pattern information processing, (3) Distributed computer systems, and (4) Network terminal systems., See also AD772511. Report on ILLIAC IV Applications Research.
- Published
- 1974
26. ILLIAC IV Applications Research
- Abstract
During this period work was performed in the following areas: (1) Development of numerical techniques suitable for parallel processing; (2) ILLIAC IV multispectral image processing; (3) Research in distributed computational systems of heterogeneous computers; (4) Research and development of network access., See also report dated 31 Mar 1974, AD786172.
- Published
- 1974
27. Experiences with an Operational Associative Processor
- Abstract
A space object position prediction program was implemented on the STARAN associative array processor (AP) installed at the Rome Air Development Center (RADC), New York. This document outlines the experience gained from this task. A section is devoted to an analysis of the time and effort required to implement the program. Emphasis is given to the program design and array layout phase. Systematic (i.e., independent of the specific program) and application- related capabilities and limitations are discussed. An analysis of the RADCAP system from a user's viewpoint is also presented. The latter part of the paper deals with recommendations for an approved STARAN system (hardware and software) and an improved host computer interface.
- Published
- 1974
28. A Critical Review of the Numerical Solution of Navier-Stokes Equations.
- Abstract
The mathematical foundation and the various practical aspects of the numerical solution of gas dynamic equations are critically reviewed with emphasis on obtaining quantitatively accurate solutions for application in various engineering and sciences. Computational stability rate of convergence and accuracy (or error estimate) are discussed. The promises and problems of the 4th generation computers are outlined within this perspective. Computational stability shoud not be obtained at the sacrifice of the convergence rate to and the accuracy of the final solution. With accuracy in mind, the explicit algorithms are likely preferrable to the implicit ones. Strict conservation of the difference formulation is recommended and exemplified to avoid the accumulation of local truncation errors and to facilitate the estimate of the errors in a steady state solution. Illustrative examples are given including supersonic flows with shocks. (Author)
- Published
- 1974
29. Pitch and Voicing in Speech Digitization.
- Abstract
A critical element of any low or medium bit rate (< 16 kbps) speech digitization system is the pitch extraction and voicing mechanism. Any digitization system in this low to medium bit rate region will require a good pitch extraction technique as a key part of the system. In this study previous pitch extraction techniques are reviewed in the light of current pitch extraction requirements for speech digitization. Two promising new pitch extraction algorithms are suggested: the multiband pitch period estimation technique and the skip-sample recursive least squares pitch position estimation technique. The former gives only spacings between pitch pulses, while the latter gives registration of the pitch pulses with the speech waveform.
- Published
- 1974
30. Order of Vector Recurrences with Application to Nonlinear Iteration, Parallel Algorithms, and the Power Method
- Abstract
The behavior of the vector recurrence y sub (n+1) = M(y sub n) + w sub (n+1) is studied under very weak assumptions. Let lambda (M) denote the spectral radius of M and let lambda (M) > or = 1. Then if the w sub n are bounded in norm and a certain subspace hypothesis holds, the root order of the (y sub n) is shown to be lambda (M). If one additional hypothesis on the dimension of the principal Jordan blocks of M holds, then the quotient order of the (y sub n) is also lambda (M). The behavior of the homogeneous recurrence is studied for all values of lambda (M). These results are applied to the analysis of: Nonlinear iteration with application to iteration with memory and to parallel iteration algorithms; Order and efficiency of composite iteration; The power method., Prepared in cooperation with Arizona State Univ., Tempe. Dept. of Mathematics. Sponsored in part by National Aeronautics and Space Administration, Langley Station, Va. Langley Research Center. Grant NGR-47-102-001.
- Published
- 1974
31. Preprocessing Cones: A Computational Structure for Scene Analysis.
- Abstract
The rough design of a semantically directed vision processor has been presented in an earlier paper. The current paper outlines the progress in developing the stages of early visual processing in that system. It describes a parallel structure, a computational 'preprocessing cone,' which transforms and reduces large amounts of visual data in a layered fashion.
- Published
- 1974
32. Parallel Algorithms for Solving Triangular Linear Systems with Small Parallelism
- Abstract
The problem of solving triangular linear systems of size n on a parallel computer with small parallelism is considered. Assume that the time is measured by the number of parallel steps of any arithmetic operation. It is shown that the problem can be done in time n squared/k + O(n) with k processors for k < or = O(n), O(n sup (2-r) log n) with O(n sup r) processors for 1 < r < 3/2, and O(n sup (1-r/3) (log sup 2)n) with O(n sup r) processors for 3/2 < or = r < or = 3. The results are obtained by using two principles of reducing parallel algorithms with large parallelism to parallel algorithms with small parallelism. The two principles for the reduction are expected to be useful for other problems., Sponsored in part by Institut de Recherche d'Informatique et d'Automatique, Le Chesnay (France).
- Published
- 1974
33. Symposium on Constructive and Computational Methods for Differential and Integral Equations Held at Indiana University, Bloomington, Indiana on February 17-20, 1974.
- Abstract
Contents: The discrete-ordinates method for the transport equation; The numerical solution of the equations for rotating stars; Automatic solution of differential equations; Integral operators for parabolic equations and their application; Galerkin methods for modeling gas pipelines; The application of sparse matrix methods to the numerical solution of nonlinear elliptic partial differential equations; Collocation solutions of integro-differential equations; On Dirichlet's problem for quasilinear elliptic equations; The numerical solution of some elliptic boundary value problems by integral operator methods; Iterative schemes for elliptic systems; Extrapolation in the finite element method with penalty; Transonic design in two dimensions; Approximate regularized solutions to improperly posed linear integral and operator equations; A majorization technique for hyperbolic equations; Boundary layer methods for ordinary differential equations with small coefficients multiplying the highest derivatives; Fixed point iterations using infinite matrices, 2; The line method for parabolic differential equations, problems in boundary layer theory and existence of periodic solutions; An integral equation method for generalized analytic functions; Solving partial differential equations using ILLIAC 4., Report on Lecture Notes in Mathematics, v430. Library of Congress Catalog Card No. 74-28189.
- Published
- 1974
34. Working Papers in Speech Recognition, 3
- Abstract
The report is a collection of Working Papers in Speech Recognition on the following topics: Organization of the HEARSAY II speech understanding system; The DRAGON system -- an overview; Parameter-independent machine segmentation and labeling; A new time-domain analysis of fricatives and stop consonants; Sub-lexical levels in the HEARSAY II speech understanding system; Inference and use of simple predictive grammars; Real-time linear predictive coding of speech on the SPS-41 microprogrammed triple-processor system; A 16-bit A-D-A conversion system for high-fidelity audio research., Sponsored in part by DARPA. See also report dated Aug 1973, AD0770633.
- Published
- 1974
35. A Study of Information in Multiple-Computer and Multiple-Console Data Processing Systems.
- Abstract
This report documents the achievements from 1 July 1973 to 1 July 1974 of continuing research for the development and application of mathematical techniques for the analysis and optimization of computer systems. The material covers the following areas: performance evaluation, parallel processing, data management systems, associative processors, languages for parallel processors, machine instruction sets.
- Published
- 1974
36. Extraction of Syntactic Features within an Array Processor.
- Abstract
The purpose of this thesis was to devise algorithms for the extraction of syntactic features within a binary-valued array processor with small neighborhoods. Simulations demonstrated the success of these algorithms and emphasized the advantages of keeping image processing within the parallel part of a recognition system.
- Published
- 1974
37. Automatic Data Processing Techniques for Graphic-Data Display Generation and Analysis.
- Abstract
Research under this grant was concerned with computer graphics and image processing, and consisted of the following 7 specific investigations: (1) development of efficient algorithms for line-drawing processing, (2) optimum two-dimensional layout, (3) discrete-time systems with parallel processes, (4) solution of the hidden-line problem for curved objects, (5) data structures for computer graphics, (6) the computer reconstruction or three-dimensional objects from multiple two-dimensional projections, and (7) detection of edges in noisy photographs. A list of publications resulting from the work is included.
- Published
- 1974
38. On the Efficient Computation of Recurrence Relations.
- Abstract
A new parallel algorithm for the solution of a general linear recurrence is described. Its relation to the work of Kogge and Stone is discussed., Sponsored in part by Grant NSF-GJ-32111.
- Published
- 1974
39. Computer Program Description - A Long Period Array Processing Package for ILLIAC IV
- Abstract
This document describes a preliminary version of a long period array processing package designed around the FKCOMB algorithm for use on the ILLIAC 4 computer. FKCOMB is a general-purpose array-processing program that uses frequency-wavenumber analysis to produce a bulletin which lists signal detections and various statistics for each detection. Two data editing and reformatting modules prepare the seismic data for FKCOMB and can be modified for use with other seismic algorithms. Preliminary reformatting of the seismic data is performed by DEM1. The data is edited and fast fourier transformed by DEM2. The input parameters required for operating these programs and their subroutines are described in this document.
- Published
- 1974
40. A Study of the ILLIAC IV Computer for Seismic Data Processing
- Abstract
Two features of the ILLIAC IV system at NASA/Ames are particularly appropriate to the processing of seismic data. One is its ability to apply a given algorithm to sixty-four different data streams simultaneously, thus providing an order of magnitude increase in processing speed over conventional machines. The second is its large data storage. The seismological algorithms for convolution filtering, beamforming, matched filtering, PHILTRE, maximum likelihood, and FKCOMB are each able to take advantage of these features in the processing of seismic data. The data can be arranged so that each processing element contains successive time windows on a given trace, as in bandpass filtering, or successive beam sets, as in beamforming.
- Published
- 1974
41. Parallel Rootfinding Algorithms.
- Abstract
Algorithms to find a simple root alpha of a continuous function f are considered which are suitable for implementation on an array type of parallel processing computer using N processing elements. (Modified author abstract)
- Published
- 1974
42. Implementation of Finite Difference Schemes of Solving Fluid Dynamic Problems on ILLIAC 4
- Abstract
The reason for building the ILLIAC 4 is to provide a computer which lends itself to the solution of partial differential equations, to matrix manipulation, as well as to solutions of other problems. ILLIAC 4 consists of a set of 64 processing elements (PE's) which follow a single instruction sequence under the control of a control unit. Each PE has its own memory, but communication between PE's is provided through a special routing register. The user of ILLIAC must recognize these constraints and special properties and be willing to expend some effort in order to use the machine effectively for a particular problem. A reasonable approach to solving problems on this computer, to do preliminary experiments, developments, and debugging on a conventional computer, and then implement a 'refined' version of the computer program on ILLIAC 4 itself. (Author)
- Published
- 1974
43. A Study of One Structure of Central Multiprocessing Unit
- Abstract
Edited trans. of Upravlyayushchie Sistemy i Mashiny (USSR) v1 n2 p89-94 Mar-Apr 73, by Victor Mesenzeff.
- Published
- 1974
44. Extended Controlled Table Arrays.
- Abstract
A generative 2-dimensional rectangular array model which allows for growth only along the edges is proposed. The growth takes place in parallel, restricted by tables, and growth along the four different edges is controlled by a control set. A special class of these models includes 2-dimensional developmental systems; the hierarchy within this class is studied. The generative power of the new model is compared with that of earlier array models.
- Published
- 1974
45. Semi-Annual Technical Report, 1 Apr-30 Sep 1973
- Abstract
During this period there was research in the following areas: Development of numerical techniques suitable for parallel processing in the areas of linear programming, algebraic eigenvalue, and approximation of functions; ILLIAC 4 multispectral image processing; enhancements to the PEESPOL compiler; network terminal systems project; and, distributed computational systems of heterogeneous computers., See also report dated 1 May 1973, AD763290. Report on ILLIAC IV Applications Research.
- Published
- 1973
46. CELLULAR REALIZATION OF THE DYNAMIC PROGRAMMING ALGORITHM.
- Abstract
General algorithmic specification, not including detailed logical design, of a highly parallel, specially organized cellular machine to embody a discrete Kalman filter is described. Various matrix operation algorithms and comparisons to sequential operations are given. Parallel computation is based on a square array of identical, limited capability modules, providing inherent speed and taking advantage of current LSI technology. The time to process increases about linearly with problem size rather than as the cube. Simulation results of a tracking problem posed by Naval Electronics Laboratory, San Diego, are included. The problem is one of a linear plant with a nonlinear observation. Thus a dynamic linearization of the observation matrix is required, such dynamics pervading the entire filter. (Author)
- Published
- 1968
47. The Design and Performance Reliability of Computers and Their Air Force Applications
- Abstract
The report summarizes the results of a two-year research program undertaken to investigate aspects of reliability of computer systems particularly with regard to theoretical aspects of their design and performance in Air Force applications. Major portions of the work were concerned with theoretical studies of image processing, pattern recognition, and computer models of unknown systems (identification). However, some studies investigated design of reliable logical hardware, computer software, and multiprocessor resource allocation modes.
- Published
- 1972
48. Naval Research Logistics Quarterly. Volume 20, Number 4.
- Abstract
Contents: Generalized multicomponent systems under cannibalization; A Bayesian approach to demand estimation and inventory provisioning; Readiness and the optimal redeployment of resources; On max-min problems; A theory of ideal linear weights for heterogeneous combat forces; Decision rules for attacking targets of opportunity; Target selection in lanchester combat: linear- law attrition process; An N-step, 2-variable search algorithm for the component placement problem; Parametric linear programming: some special cases; Sequential search of an optimal dosage: non-Bayesian methods; Further light on nonparametric selection efficiency; Alternate methods of project scheduling with limited resources; Scheduling with parallel processors and linear delay costs., See also Volume 20, Number 3, AD-772 444.
- Published
- 1973
49. The Effects of Concurrency Control on Database Management System Performance
- Abstract
The main goal of this thesis is to study the performance tradeoffs between parallelism and increased concurrency control overhead during simultaneous user updates of a database. During such updates, a database management system must guarantee that the multiple users do not interfere with each other. The potential advantages of parallelism in accessing a database include the better utilization of computer resources and better response times for users. Those advantages, however, may be offset by the increased use of system resources to insure that there is no interference between the multiple users. In a distributed database, the data is stored on different computer sites connected through some type of network. In a distributed database, increased parallelism is possible during simultaneous database activities. However, the concurrency control overhead may also increase. The simulations modeled a variety of concurrency control algorithms to study the additional tradeoffs in a distributed database. The simulation results indicated that with a high speed network and mostly local database activities, either concurrency control approach is acceptable. As the network becomes slower, the decentralized control algorithms are preferable. If most of the database activities are distributed, however, the primary site approach can take advantage of its global knowledge to better schedule the processing of transactions and thus provide better performance than the decentralized algorithms.
- Published
- 1970
50. Perceptrons and Pattern Recognition
- Abstract
This monograph includes most of the results to date of our analysis of the geometric ability of linear separation machines. We expect soon to publish the complete work as a book: the complete version will contain further results on learning and on some relation between parallel and serial algorithms. Topics include: Algebraic Theory--Theory of Boolean linear separation functions, Group theory of linear predicates, Some special predicates, and The 'And-Or' Theorem; Geometric Theory--Connectivity and topological properties, Geometric patterns of low order, Normalization and stratification, and The Diameter- limited perceptron; and Magnitude of the Coefficients.
- Published
- 1967
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