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The use of the majority (2 out of 3) logic element in anticipated carries for adders, multipliers, etc., yields very fast designs with only a moderate number of gates. The general theory of such carries is presented. This is applied to the design of a 48-bit adder. One hundred and sixty-four majority gates give carries for all 48 bits with a maximum of 6 stages of delay. The relationship between delay and quality of gates required is plotted.