Search

The document describes research activities in progress under Project CIDS through which a model operational chemical information and data system was developed. The document discloses the present state of CIDS file building and reports the successful incorporation of the revised chemical search screens into the system and the establishment of chemical specifications for handling certain currently inadmissible classes of compounds. Various improvements in search and file building techniques are reported, including an acceptable method for analyzing complex ring systems, and the status of R and D with the cathode ray tube as an input-output device is described. Also included are reports of recent CIDS computer documentation and a description of the formal CIDS No. 7 report on query formulation and encoding.

A passive damping method for aligning the instantaneous spin, symmetry and angular momentum axes of a solid, axially symmetric almost spherical satellite gyro is analyzed. Damping is accomplished by the dissipation of energy due to cyclic strains in the gyro body caused by its torque-free precession. Damping is calculated for a particular gyro design. (Author)

The purpose of the subject contract was to develop fault isolation test procedures for FADAC circuit boards expressed in FATAL II compiler language. A number of these test procedures were completed. However, only one circuit was finished to the point where it was run through the compiler. The input and output of the compiler for this test procedure is contained in the appendix. One of the difficulties encountered in this project was the shortage of test points in certain FADAC circuit boards. This is pointed out in Table 1 which shows that the number of test points contained in these 31 circuit boards varies from a low of zero to a high of 49. Another difficulty has been the specification of component parameter values. The manufacturer's specifications although probably suitable for production acceptance testing for individual components are very often not appropriate for in-circuit fault isolation testing. Table 2 summarizes some of the work done over the past 5 years on fault isolation test procedures for 14 circuits of both the Vacuum Tube and Solid State types. The number of parameters in these circuits varied from 9 for the simplest circuit to 386 for the Logic Flip Flop circuit. (Author), Available only for reference use at DDC field services. Copy is not available for public sale. See also AD-603 135, AD-603 136, AD-605 224.

Contents: Research guidelines for digital computer-controlled system for checkout and fault isolation Computer techniques for solving electric circuits for fault isolation Simplified explicit solution of networks with two internal nodes Explicit method of solution for single-element-kind networks Properties of linear graphs based on trees Bounds for the maximum number of trees in a graph Evaluation of network determinants via the key subgraph Conditions for network-element-value solvability Statistical considerations in element value solutions Solution procedure for single-element-kind network Converse of the star-mesh transformation Formulas for the number of trees in a network

The FATAL II compiler-assembler system was specifically designed for use on automatic checkout and automatic testing problems. Since the object computer in the wide variety of automatic checkout systems being developed presently could be any one of a number of existing computers or machines not yet developed, the FATAL II system was designed so that it would not obsolesce due to changes in the object computer. This is done by permitting the compiler to output assembler language. The assembler, in a second pass, then generates object machine code. Thus, only the assembler need be modified when a different object computer is used. This is a relatively trivial task. In order to allow for generality in the selection and specification of verbs, the FATAL II compiler is partially a syntax directed compiler and has been designed so that the compilation may be carried out at the maximum possible speed. The compiler section of the manual is intended for use by electronic circuit analysts, test program designers, and technicians. The assembler section is written for use by programmers.