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Abstract 3D neuromorphic hardware system is first demonstrated in neuromorphic application as on‐chip level by integrating array devices with CMOS circuits after wafer bonding (WB) and interconnection process. The memory window of synaptic device is degraded after WB and 3 Dimesional (3D) integration due to process defects and thermal stress. To address this degradation, Ag diffusion in materials of Ta2O5 and HfO2 is studied in a volatile memristor, furthermore, the interconnection and gate metal Ru are investigated to reduce defective traps of gate interface in non‐volatile memory devices. As a result, a memory window is improved over 106 in both types of devices. Improved and 3D integrated 12 × 14 array devices are identified in the synaptic characteristics according to the change of the synaptic weight from the interconnected Test Element Group (TEG) of the Complementary Metal Oxide Semiconductor (CMOS) circuits. The trained array devices present recognizable image of letters, achieving an accuracy rate of 92% when utilizing a convolutional neural network, comparing the normalized accuracy of 93% achieved by an ideal synapse device. This study proposes to modulate the memory windows up to 106 in an integrated hardware‐based neural system, considering the possibility of device degradation in both volatile and non‐volatile memory devices demonstrated by the hardware neural system.

Abstract The rapid advancement of AI‐enabled applications has resulted in an increasing need for energy‐efficient computing hardware. Logic‐in‐memory is a promising approach for processing the data stored in memory, wherein fast and efficient computations are possible owing to the parallel execution of reconfigurable logic operations. In this study, a dual‐logic‐in‐memory device, which can simultaneously perform two logic operations in four states, is demonstrated using van der Waals ferroelectric field‐effect transistors (vdW FeFETs). The proposed dual‐logic‐in‐memory device, which also acts as a two‐bit storage device, is a single bidirectional polarization‐integrated ferroelectric field‐effect transistor (BPI‐FeFET). It is fabricated by integrating an in‐plane vdW ferroelectric semiconductor SnS and an out‐of‐plane vdW ferroelectric gate dielectric material—CuInP2S6. Four reliable resistance states with excellent endurance and retention characteristics were achieved. The two‐bit storage mechanism in a BPI‐FeFET was analyzed from two perspectives: carrier density and carrier injection controls, which originated from the out‐of‐plane polarization of the gate dielectric and in‐plane polarization of the semiconductor, respectively. Unlike conventional multilevel FeFETs, the proposed BPI‐FeFET does not require additional pre‐examination or erasing steps to switch from/to an intermediate polarization, enabling direct switching between the four memory states. To utilize the fabricated BPI‐FeFET as a dual‐logic‐in‐memory device, two logical operations were selected (XOR and AND), and their parallel execution was demonstrated. Different types of logic operations could be implemented by selecting different initial states, demonstrating various types of functions required for numerous neural network operations. The flexibility and efficiency of the proposed dual‐logic‐in‐memory device appear promising in the realization of next‐generation low‐power computing systems.

A Dual-Edge-Triggered (DET) flip-flop (FF) that can reliably operate at low voltage is proposed in this paper. Unlike the conventional Single-Edge-Triggered (SET) flip-flops, DET-FFs can improve energy efficiency by latching input data at both clock edges. When combined with aggressive voltage scaling, significant efficiency improvement is expected. However, prior DET-FF designs were susceptible to Process, Voltage and Temperature (PVT) variations, limiting their operation at low voltage regimes. A fully static true-single-phase-clocked DET-FF is proposed to achieve reliable operation at voltages as low as a near-threshold regime. Instead of the two-phase or pulsed clocking scheme in conventional DET-FFs, a True-Single-Phase-Clocking (TSPC) scheme is adopted to overcome clock overlap issues and enable low-power operation. Fully static implementation also enables robust operation in a low voltage regime. The proposed DET-FF is designed in 28nm CMOS technology, and a comprehensive analysis including post-layout Monte Carlo simulation for wide PVT ranges is performed to validate the design approaches. Extensive analysis and comparison with prior-art DET-FFs confirmed that the proposed DET-FF can operate at the lowest voltage of 0.28 V for a temperature range of -40 °C to 120 °C while maintaining nearly-best energy efficiency and power-delay-product.

This paper describes a voltage-mode transmitter that stacks independent non-return-tozero (NRZ) and four-level pulse amplitude modulation (PAM4) drivers for dual channels. The stacked structure can improve the transmitter's power efficiency owing to its current-recycling capabilities. The PAM4 voltage-mode driver with voltage regulators, implemented to increase data rates, generates multilevel signals. The proposed dynamic load control inside the PAM4 driver minimizes the voltage variation in the output of the regulators, which is caused by the variations of the data patterns. A prototype chip was fabricated using a 28-nm CMOS process. The stacked 7-Gb/s NRZ and 14-Gb/s PAM4 transmitters have achieved a full aggregate transmission rate of 21 Gb/s while consuming 12.6 mW from a 1-V power supply. When transmitting 500-mVpp signals with the proposed transmitter through 2-cm FR4 channels, the eye heights obtained in the NRZ and PAM4 channels were 312 and 92 mV, respectively.

A novel harvesting interface for multiple piezoelectric transducers (PZTs) is proposed for high-voltage energy harvesting. Pre-biasing a PZT prior to its mechanical deformation increases its damping force, resulting in higher energy extraction. Unlike the conventional harvesters where a PZT-generated output is assumed to be continuous sinusoidal and output polarity is assumed to be alternating every cycle, PZT-generated output from human motion is expected to be random. Therefore, in the proposed approach, energy is invested to the PZT only when PZT deformation is detected. Upon the motion detection, energy stored at a storage capacitor (CSTOR) from earlier energy harvesting cycle is invested to pre-bias PZT, enhancing energy extraction. The harvested energy is transferred to back CSTOR for energy investment on the next cycle and then excess energy is transferred to the battery. In addition, partial electric charge extraction (PECE) is adapted to extract a partial amount of charges from the PZT every time its voltage approaches the process limit of 40 V. Simulations with 0.35 µm BCD process show 7.61× (with PECE only) and 8.38× (with PECE and energy investment) improvement compared to the conventional rectifier-based harvesting scheme Proposed harvesting interface successfully harvests energy from excitations with open-circuit voltages up to 100 V.

A fully integrated piezoelectric energy harvesting interface is proposed for harvesting energy from irregular human motion. To handle irregular pulse inputs generated by the piezoelectric transducer (PZT), the proposed harvesting interface includes a wake-up controller that activates the harvesting interface only when human motion is detected and deformation is applied on the piezoelectric material, thereby keeping static power loss low. The PZT output voltage is increased to its peak voltage by removing any type of external load capacitance seen by the PZT during its deformation. Once the peak voltage is detected, a multi-voltage conversion-ratio-based switched-capacitor circuit is activated to transfer PZT-generated energy to the battery in multiple ratio steps to maximize the conversion efficiency, with the help of a carefully designed harvesting controller. To deal with open-circuit voltages (VOCS) higher than the maximum voltage tolerated (VMAX) by available technology, capacitive partial electric charge extraction is activated every time the PZT output voltage approaches the VMAX. The proposed harvesting interface extracts 3.37 times more energy than a conventional full-bridge rectifier-based harvesting scheme.

An energy-harvesting interface for kinetic energy harvesting from high-voltage piezoelectric and triboelectric generators is proposed in this paper. Unlike the conventional kinetic energy-harvesting interfaces optimized for continuous sinusoidal input, the proposed harvesting interface can efficiently handle irregular and random high voltage energy inputs. An N-type mosfet (NMOS)-only power stage design is introduced to simplify power switch drivers and minimize conduction loss. Controller active mode power is also reduced by introducing a new voltage peak detector. For efficient operation with potentially long intervals between random kinetic energy inputs, standby power consumption is minimized by monitoring the input with a 43 pW wake-up controller and power-gating all other circuits during the standby intervals. The proposed harvesting interface can harvest energy from a wide range of energy inputs, 10 s of nJ to 10 s of µJ energy/pulse, with an input voltage range of 5−200 V and an output range of 2.4−4 V under discontinuous as well as continuous excitation. The proposed interface is examined in two scenarios, with integrated power stage devices (maximum input 45 V) and with discrete power stage devices (maximum input 200 V), and the harvesting efficiency is improved by up to 600% and 1350%, respectively, compared to the case when harvesting is performed with a full bridge rectifier.

An output capacitor-less low-dropout (OCL-LDO) regulator with a wide range of load currents is proposed in this study. The structure of the proposed regulator is based on the flipped-voltage-follower LDO regulator. The feedback loop of the proposed regulator consists of two stages. The second stage is turned on or off depending on the variation in the output load current. Hence, the regulator can retain a phase margin at a wide range of load currents. The proposed regulator exhibits a better regulation performance compared to the ones in previous studies. The test chip is fabricated using a 65-nm CMOS process.

Advancements in low power circuits and batteries have enabled the design of miniature sensors with tiny batteries. In such systems, implementing dynamic voltage scaling (DVS) is crucial for maximizing system lifetime. In this paper, a new switched capacitor (SC) converter that is capable of handling a wide range of load currents and output voltages is presented for on-chip DVS implementation. The proposed converter consists of multi-ratio multi-leaf SC stages and reconfigurable interconnect, enabling fine voltage resolution. The stage interconnect scheme enables cascaded or parallel connection of stages. The multi-leaf structure allows load-dependent switch size selection, offering a better trade-off between losses over a wide load range. A limited-voltage-swing switch-driving scheme allows efficient down-conversion from high battery voltage input. A prototype was fabricated in a 180 nm process, providing an output voltage with effective resolution of 16 mV over a load current range of 300 nA to 300 μA (1000×) from a 4 V battery. Efficiency greater than 62% and a peak efficiency of 77% are achieved under a light load (500 nA) over a voltage range of 400 mV to 1.6 V. Efficiency greater than 64% and a peak efficiency of 72% are achieved under a heavy load (200 μA) over a voltage range of 700 mV to 1.6 V.