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A 256-Mb gate-all-around (GAA) 6T SRAM is implemented in Samsung 3GAE EUV technology. Adaptive dual-bitline (ADBL) and adaptive cell-power (ACP) SRAM assist schemes are proposed to reduce SRAM ${V_{{MIN}}}$ . ADBL reduces the effective bitline (BL) resistance up to 62% by connecting auxiliary bitline (AUXBL) of small resistance to BL in the write operation. ACP performs write assist by selecting a farther power switch from the accessed bitcell to improve write margin with the increased cell-power resistance. Silicon shows that both ADBL and ACP improve ${V_{{MIN}}}$ by 230 mV.

We have proposed a current mirror-based level shifter (LS) with a logic error detection (CMLS-LED), which is capable of converting a near-threshold signal to a super-threshold signal. The proposed CMLS-LED resolves the current contention problem observed in the conventional cross-coupled pFET-based LS (CPLS) by using the current mirror and removes the static current in the conventional current mirror LS with adopting the feedback pFET controlled by the output node. Compared with Wilson’s current mirror-based LS (WCMLS), CMLS-LED offers an enhanced speed by avoiding the threshold voltage drop of the feedback pFET and is free from the stability issue due to an incomplete output swing. Measurement results obtained from the test chip fabricated with 14-nm finFET technology, in which CMLS-LED is implemented with WCMLS, CPLS, and Osaki’s LS, shows that the proposed CMLS-LED can widen the operating voltage range by 200 mV compared wth the CPLS, along with a speed improvement of 80%, when compared to WCMLS.

An embedded level-shifting (ELS) dual-rail SRAM is proposed to enhance the availability of dual-rail SRAMs. Although dual-rail SRAM is a powerful solution for satisfying the increasing demand for low-power applications, the enormous performance degradation at low supply voltages cannot meet the high-performance cache requirement in recent computing systems. The requirement of many level shifters is another drawback of the dual-rail SRAM because it degrades the energy-savings. The proposed ELS dual-rail SRAM achieves energy-savings by using a low supply voltage to precharge bitlines while minimizing the performance overhead by appropriately assigning a high-supply voltage to critical circuit blocks with effective level-shifting circuits. The sense amplifier embeds a level-shifting operation, thereby operating with a high supply voltage for a fast sensing operation. The proposed dynamic output buffer resolves the potential static current problem and improves the read delay. The number of level shifters is reduced using a proposed write driver, which conducts level-shifting and write-driving simultaneously. The proposed ELS dual-rail SRAM achieves low-power operation with 71.4% power consumption compared to single-rail SRAM with 72% performance overhead in circuit-level simulation, while the previous hybrid dual-rail SRAM shows 67.8% energy consumption with 270% performance overhead. In architecture-level simulation using Gem5 simulator with SPEC2006 benchmarks, the system with the ELS dual-rail SRAM caches shows, on average, 29% performance improvement compared to that of the system with the hybrid dual-rail SRAM caches.

This paper proposes a complete and full automation framework of evaluating design rules (DRs) to facilitate the process of design technology co-optimization (DTCO), which is highly demanded in 14-nm and beyond technologies. Our proposed framework explores the changes of DRs and evaluates the impacts on the number and types of DR violations as well as the resulting cell/chip layout area. Precisely, the core engine of our DR evaluation framework for DTCO, the automatic cell layout generator, consists of key enabling techniques for standard cell layout optimization. They are integrated coherently to seamlessly support the advanced process technologies using FinFET transistors, complex DRs, and double patterning (DP) lithography. Also, the tight integration of our automatic cell layout generation into the DR evaluation framework with diverse analysis features enables the DTCO process to be much faster and more efficient. We provide a set of experimental data not only to show how much our proposed enabling techniques are effective in optimizing layouts but also to show how effectively our framework explores and analyzes the DTCO parameters (e.g., ground DRs and DP DRs).

Bitline (BL) charge-recycling-based static random access memory (SRAM) write assist circuits (BCR-WA) are proposed to reduce the minimum operating voltage ( $V_{\mathrm {MIN}}$ ) of SRAM. In the proposed schemes, the charges stored on the unselected BL are utilized to raise the cell ground voltage (VSS) of the selected bit cell, and the increased cell VSS (CVSS) enhances the write ability. According to the metal routing direction of CVSS in the layout, two types of BCR-WA are proposed, BCR-WA for vertical CVSS routing (BCR-WA $_{\mathrm {V}}$ ) and horizontal CVSS routing (BCR-WA $_{\mathrm {H}}$ ). To evaluate the proposed circuits, HSPICE simulations are performed and the test chip is implemented using a 14-nm FinFET technology. Thanks to the charge-recycling operation, BCR-WAV and BCR-WAH can save energy by 11%–44% and 30%–66%, respectively, compared to the previous write assist circuits, with a comparable or less area overhead and an insignificant degradation in read performance ( $V_{\mathrm {MIN}}$ by 150 mV. In particular, silicon measurement result for BCR-WAH proves an 125-mV improvement in $V_{\mathrm {MIN}}$ .

A 28nm embedded Flash memory in this paper is designed for the Automotive application in Foundry. Through Temperature Auto-Tracking Sense Amplifier using the Bit line Charge Boost (BCB) and Bit line Leakage current Compensation (BLC) technology, it succeeded in implementing under 10ns read operation (>100MHz) and size improvement (7.42Mb/mm2). Also Word Line and YMUX Gate Boost (WYGB) is applied to secure a sensing margin at a low voltage (0.85V). These techniques enable 10ns reading operation of 288 bits (26.8Gb/s) at a time based on 16Mb memory size by improving sensing margin in temperature range of -40~150’C. It also implemented a competitive minimum IP size and we have secured high yield that enough to mass production as a result of Silicon validation. Based on competitive advantage through technology differentiation, it will be provided to various customers in all eFlash IP Foundry markets including Automotive business.

Voltage Auto Tracking Cell Power Lowering (VACPL) Write Assist circuit is proposed for low-power SRAM with dual-rail architecture. VACPL adaptively controls the cell voltage with respect to the dual rail offset voltage to maximize bitcell write-ability. A 5nm EUV FinFET test chip demonstrates 210mV VMIN improvement and 4.7x larger range of operating voltage with VACPL. The proposed VACPL and VATA achieves 95.2% leakage power reduction by lowering VDDC by 400mV in 5nm 5G mobile device.

This paper presents SRAM write- and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.

Advanced technologies help to improve SRAM performance via recent transistor breakthroughs [1], which allow SRAM designers to focus on handling metal resistance by alleviating device performance impediments. Since SRAM margins are more vulnerable to the increasing metal resistance, due to smaller critical dimensions, SRAM-assist circuits are proposed to overcome the impact of metal resistance in recent technologies [2 –5]. One of the challenges is the design limitation such as the quantized transistor, which requires SRAM-assist to optimize SRAM margins. In this paper, gate-all-around (GAA) SRAM design techniques are proposed, which improve SRAM margins more freely, in addition to power, performance, and area (PPA). Moreover, SRAM-assist schemes are proposed to overcome metal resistance, which maximizes the benefit of GAA devices.