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Low-power consumption is becoming a crucial concern that cannot be neglected in system-on-chip (SoC) designs. Low-power solutions help designers to provide a powerful methodology to analyze, estimate, and optimize today’s power concerns. Early estimation of power at a high level reduces the redesign cycle and turn-around time. Power dissipation is a function of input patterns and their characteristics. This paper describes a power estimation technique by using predefined statistical characteristics-based input patterns, which gives the average power dissipation of individual intellectual property (IP) blocks and interconnects/buses in an SoC system design. During the power estimation phase, the discrete water cycle algorithm is implemented to generate optimized input patterns. Then Monte-Carlo zero-delay simulation approach is used for each individual IP block and buses at a high level. Total system power is the simple addition of average powers of IP blocks and buses. In experiments of entire IP-based SoC system with buses, our modified macromodel gives an average error of 7.91%. Accuracy of the proposed model is improved as compared to our previous model. [ABSTRACT FROM AUTHOR]