293 results on '"Poncino, M."'
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2. Channel-wise Mixed-precision Assignment for DNN Inference on Constrained Edge Nodes
3. A Parallel Approach to Symbolic Traversal based on Set Partitioning
4. Dual-[formula omitted] assignment policies in ITD-aware synthesis
5. Implementation of a thermal management unit for canceling temperature-dependent clock skew variations
6. Thermal-aware clock tree design to increase timing reliability of embedded SoCs
7. Architectural leakage power minimization of scratchpad memories by application-driven subbanking
8. A Parallel Approach to Symbolic Traversal based on Set Partitioning
9. A Semi-Empirical Model of PV Modules Including Manufacturing I-V Mismatch
10. A study of the resetability of synchronous seqeuntial circuits
11. SystemC-AMS Simulation of Energy Management of Electric Vehicles
12. CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
13. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits
14. A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions
15. Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks
16. IR-Drop Analysis of Graphene-Based Power Distribution Networks
17. Modeling of thermally induced skew variations in clock distribution network
18. THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future
19. Power-Gating: More Than Leakage Savings
20. Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models
21. Enabling concurrent clock and power gating in an industrial design flow
22. Energy-Efficient Encoding for Secure Digital LCD Interfaces
23. Current-Controlled Battery Management Policies for Lifetime Extension of Portable Systems
24. SystemC Co-Simulation and Emulation of Multi-Processor Systems-on-Chip
25. An RTL Power Estimation Tool with On-Line Model Building Capabilities
26. Area and Timing Models for PTL Macrocells
27. Analysis of Energy Dissipation in Cache Memories
28. Symbolic Optimization of FSM Networks Based on Redundancies Identification and Removal
29. A Library of Accurate Battery Models for Usage in High-Level Power Estimation and Optimization
30. Combinational Characterization-Based Power Macro-Models for Sequential Macros
31. A cross-level verification methodology for digital IPs augmented with embedded timing monitors
32. Fondamenti di Informatica: 100 Esercizi d'Esame Svolti
33. Power estimation of behavioral descriptions
34. SMAC: Smart Systems Co-design
35. Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control
36. IR-drop analysis of graphene-based power distribution networks
37. Application-specific memory partitioning for joint energy and lifetime optimization
38. On-chip process variation-tracking through an all-digital monitoring architecture
39. System level techniques to improve reliability in high power microcontrollers for automotive applications
40. Partitioned cache architectures for reduced NBTI-induced aging
41. Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems
42. Dual- assignment policies in ITD-aware synthesis
43. A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits
44. Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits
45. Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching
46. Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating
47. Thermal-Aware Design Techniques for Nanometer CMOS Circuits
48. Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis
49. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits
50. A scalable algorithmic framework for row-based power-gating
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