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In this study, a thin-film transistor with a heterogeneous channel structure was introduced into oxide semiconductors to improve their electrical properties, which resulted in high mobility and lower subthreshold swing (S.S.).

In this work, the suppression of hydrogen diffusion in top-gate InGaZnO thin film transistors (TFTs) was observed. Under positive-bias temperature stress, the threshold voltage in short-channel devices was negatively shifted; this shift was attributed to hydrogen diffusion. To inhibit hydrogen migration, low-temperature high-pressure (LTHP) fluorine treatment was subsequently utilized. Under supercritical fluid states, fluorine, the most electronegative species of all elements, acted as a reactant and reduced mobile hydrogen. It was confirmed that the treatment benefited the characteristic properties of InGaZnO TFTs with varied channel lengths, especially in devices with short channels. The reliability of devices under stress improved through the LTHP treatment; the effects of suppression of hydrogen diffusion were illustrated by the energy band and capacitance–voltage curves of devices. Energy-dispersive X-ray spectroscopy of the specimen treated with LTHP indicated the presence of fluorine, which ensured the contribution of the treatment. Thus, LTHP treatment enables the realization of small-sized high-performance top-gate InGaZnO TFTs.

In this work, three MISHEMT devices with different electric-field-dispersion layer (EDL) behave the same pristine electrical properties. EDL, which is low dielectric constant (low-k), can effectively disperse electric field, which enhances breakdown voltage and improves reliability in MISHEMT. In a comparison of devices with high-k and low-k EDL, the on-state current ( $\text{I}_{\mathrm{ on}}$ ) of the high-k EDL devices is more significantly reduced than low-k EDL devices after off-state stress. A model for the dispersion of electric fields by the EDL is proposed for this interesting phenomenon. The distribution of the electric field is verified by Silvaco electric field simulation. Finally, the breakdown voltages of the three devices were measured, confirming that the devices with a low-k EDL can increase their breakdown voltages by an additional 600 V, which is 250 % higher than that in the high-k EDL device.

In this work, the impact of positive bias stress (PBS) on an all copper(Cu)-electrode a-InGaZnO TFT is discussed. Commonly, Cu diffusion from the source/drain electrode after negative bias stress (NBS) leads to degradations in the on-state current and subthreshold swing. However, this study finds that diffusion in the gate insulator layer from the gate electrode suffers from more serious degradation. Eventually, this phenomenon causes a serious breakdown of the gate insulator such that it loses the transistor function. Results indicate that after 2000s of PBS, accumulation of Cu ions forms a filament which dominates the leakage path. During the stress duration, the gate leakage current is monitored and current fittings are adopted to confirm the phenomena. Furthermore, temperature dependencies have verified the results of hopping and Ohmic conduction at different stages of deterioration. Compared to previous literature that focus on the impacts of source/drain electrodes, this work suggests that gate engineering for thin film transistors is more urgent for high-quality display applications.

In this letter, a study of physical mechanisms is introduced to describe an abnormal phenomenon in transfer characteristics while p-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) were subjected to a negative bias temperature stress (NBTS) in an illuminated environment. In general, under NBTS, the transfer characteristics exhibits a negative shift of threshold voltage and a degradation of subthreshold swing. Here, however, experimental results reveal that the degree of degradation is different after NBTS is applied to poly-silicon TFTs in a darkened and in an ultraviolet condition. This variation is mainly a result of the light-generated electrons recombining with the inversed holes, and leading to a lower degree of degradation. Moreover, we found that the influence of the UV light is an edge effect at different channel lengths. This letter investigates the illumination effect in LTPS TFTs during NBTS, and the phenomenon is clarified by electrical measurements and by trap state extraction.

In this article, an n-type double-gate low-temperature polysilicon (LTPS) TFT is investigated. Previous work has confirmed that the hot-carrier effect will cause impact ionization. Here we observed that, after hot-carrier stress (HCS), the transfer curve in the saturation region has a negative $\text{V}_{\mathrm {th}}$ shift, and a hump is also observed. The reverse output characteristic shows that gate induced drain leakage (GIDL) of the transistor gradually increases and the subthreshold swing (S.S.) has a tendency to collapse. In structures with longer lightly doped drain (LDD) lengths, the electric field at both source/drain side can be effectively dispersed. Thereby, an extended LDD can reduce the overall degradation, and a physical model of explanation is proposed. By using the energy band diagram, we clarify how the additional electron hole pairs affect the output property. Next, Silvaco TCAD simulation is utilized to illustrate the electric field distribution and validate the physical model.

In this study, a novel structural device, named as a wing-shaped TFT, is proposed and is demonstrated to prevent fast deterioration under mechanical bending in foldable devices. After long-term mechanical bending, standard low-temperature polysilicon TFTs exhibit instability behaviors such as sub-channel formation, serious threshold voltage shifts, an on-current (ION) increase, and an off-current (IOFF) decrease. These phenomena are believed to be due to additional oxide traps along the channel-width edges of the gate insulator after bending. In order to suppress this degradation, a wing-shaped structure is proposed. By extending the active layer, degradation regions are shifted away from the main channel. Therefore, the reliability of the devices is enhanced. The transfer characteristics show enhanced electrical behavior after being held for 48 hours in a static bent condition, with an 88% drop in threshold voltage shift as well as a 55% decrease in subthreshold swing degradation, proving better durability of the foldable TFT to bending stress for devices with these wings. Time-dependent transfer characteristics, a COMSOL simulation, and device geometry are discussed to support our findings.

In this experiment, the electrical performance of zinc oxide based-resistive random access memory (RRAM) is successfully improved by using annealing in ammonia hydroxide solution at low-temperature and high pressure to complete ammonium-doped ZnO based-RRAM. The results of material analysis indicate that using CO2 as ammonia hydroxide carrier during the annealing process leads to the reduction in dangling bond density. This can be clearly observed in the decrease in breakdown voltage during the forming process and a lower operating current during operation. Furthermore, in this ammonium-doped ZnO based-RRAM, we study the molecular doping of NH3 in ZnO, where the endurance and retention properties are improved as well. These improvements can be attributed to the higher concentration of nitrogen in the switching layer, which can effectively control the active oxygen ions during the operation process.

In this work, the time-dependent behaviors of dual-channel amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under negative bias illumination stress (NBIS) are systematically discussed. The dual-channel comprised two different IGZO layers fabricated by tuning the oxygen flow during deposition. The presence of heterojunctions enhanced field-effect mobility by 1.5× owing to the confinement of carriers in buried channels because of an energy barrier. However, after long periods of NBIS stress, the degradation of a-IGZO TFTs resulted in the entrapment of photo-generated electron–hole pairs at interface defects. The conduction path migrated to the surface channel. Results from extracting the hysteresis window and utilizing capacitance–voltage measurements have indicated a channel migration phenomenon due to the entrapment of electrons and holes at the surface and buried channel interfaces.

This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance.

High-performance ultraviolet (UV) sensors using amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) can detect ION/IOFF ratio up to 106 and match the a-IGZO panel process. However, it has a reliability issue under long-term detection. When the top gate length of the dual gate TFT is small, it is twice as reliable as a TFT where the top gate fully covers the device. The electrical properties of the device correspond to the a-IGZO energy band, such that the top gate length was positively related to the underlying energy band diagram. The integrated systems engineering technology computer aided design (ISE-TCAD) electric field simulations show that the etch stop layer (ESL) electric field is weak in the small top gate device. This means that it is difficult for the holes to either be trapped in the ESL or to generate ionized oxygen vacancies.

In this letter, we integrated a floating bottom gate (BG) as a light shielding layer in a thin-film transistor (TFT). We observed abnormal ${I}_{D}$ – ${V}_{D}$ output characteristics and unsaturated current characteristics. In addition, drain-induced barrier lowering has a significant impact on ${I}_{D}$ – ${V}_{D}$ characteristics as the drain voltage increases. These phenomena are due to changes in electrical potential that occur due to the capacitive coupling effect. Technology computer aided design simulations explained and correlated well with our observations. Then, a physical model is proposed to verify the abnormal electrical characteristics. Grounding the BG light shield was found to provide better control over the threshold voltage and total current performance. This letter results may lead to better applications in the TFT driving circuits.

This paper analyzes the abnormal degradation induced by hydrogen annealing. Although device performance is enhanced after hydrogen annealing, an abnormal hump is observed in transfer characteristics ( ${I}_{D} - {V}_{G}$ ) under positive bias temperature stress (PBTS). Threshold voltage shift ( $\Delta \text{V}_{\text {TH2}}$ ) in this hump region increases with increasing stress voltage and temperature. Additionally, $\Delta \text{V}_{\text {TH2}}$ is independent of the channel width. A novel hydrogen rupture-diffusion model is proposed to explain the degradation. COMSOL simulation and ${C} - {V}$ measurement are utilized to clarify the precise degradation position. Moreover, variable S/D spacing ( $\text{L}_{\text {SD}}$ ) devices are designed to support the mechanism. Finally, ISE-TCAD software is carried out to verify the proposed model. Our results from electrical measurement suggest that hydrogen can cause additional instability, which shares a similar conclusion for those by using material analyzation and first-principle simulation.

This paper demonstrates the cumulative effects of compressive stress and high current stress at high temperature in flexible a-InGaZnO4 thin-film transistors. An abnormal hump can be found in the subthreshold regime in the results from a reliability test that combines high temperature and high current stress with mechanical bending at 10 mm. During this stress, holes will tend to inject into the defects in the etching stop layer near the source side, which is induced by compressive bending. A COMSOL simulation was performed and confirmed that defect generation occurs in the etching stop layer during compressive bending. Further, the path of the back-channel leakage current caused by the localized trapped holes was also confirmed by changing the width/length of thin film transistors (TFTs) in the reliability test. The precise hole trapping distribution was verified by a single side capacitance-voltage measurement and source/drain interchange measurement.

The instability of amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) under ultraviolet (UV) light was thoroughly investigated in this paper. Unlike in a darkened state, an off-state leakage current can be found in the dual-sweep I–V transfer curve of a-IGZO TFTs under UV light illumination. Furthermore, despite the same UV light condition, the forward sweep and reverse sweep show different I–V curves, representing two different physical mechanisms. First, the subthreshold swing degradation and threshold voltage shift to the negative direction in the forward sweep are due to the total channel barrier lowering and can be confirmed by changing the light exposure region. Second, in the reverse sweep, the suggested back-channel leakage current can be controlled by dual-gate TFTs. UV light exposure of the metal–insulator–semiconductor–metal structure verifies that the off-state leakage current passes through the back channel in a reverse sweep. Finally, the physical mechanism links between forward and reverse sweeps have comprehensive interpretation in this paper.

This study investigates the recovery behavior of GaN high-electron mobility transistors on SiC substrates under different hot-carrier stress conditions. The threshold voltage shifts positively due to hot electron trapping at the buffer layer under hot-carrier stress. However, the recovery between semi-on (Vt < VG < 0 V) hot-carrier stress and on-state (VG > 0 V) carrier stress is significantly different. This phenomenon is systematically discussed in terms of the applied gate voltage under stress condition, which affects the occupation of the surface donor states. After applying a semi-on hot-carrier stress, the threshold voltage continues to shift positively after relaxing the applied voltage. In contrast, the threshold voltage exponentially recovers after applying an on-state hot-carrier stress. Silvaco technology computer aided design (TCAD) simulation was performed to verify the effect of the surface donor state on the threshold voltages. Since switching between on-state and off-state in RF-applications includes both conditions, we suggest that the surface donor states are crucial to determine the failure of devices.

This study examines self-heating-related instability in n-channel low-temperature polysilicon thin-film transistors with different source/drain contact hole densities. Devices with more contact holes exhibit a higher on-current without additional parasitic capacitance, further enhancing the RC delay property. For high-current-induced self-heating stress, a device with one contact hole has one hump due to the kink effect. However, a device with six contact holes has two humps, induced by the kink effect and thermionic field emission. COMSOL simulations of heat distribution and energy bands are performed to examine the different degradation behaviors, and then physical models are proposed.

In this work, a two-step degradation phenomenon in D-mode Si3N4/AlGaN/GaN metal–insulator–semiconductor-high electron mobility transistors is discussed systematically. During off-state stress, threshold voltage shifts positively for a short duration, and is followed by a negative shift. In contrast, the off-state leakage continues to decrease throughout the entire stress. Results of varied measurement conditions indicate that carrier trapping at different regions dominates this phenomenon. It is interesting that under a large lateral electric field, electron–hole pairs are generated and will then be trapped at the gate dielectric layer. Furthermore, when increasing the stress temperature, impact ionization due to carriers from the gate electrode becomes more severe. Finally, devices with different gate insulator thicknesses are performed to verify the physical model of the degradation behavior.

In this work a novel device structure aiming to suppress the degradations under bending in flexible devices is demonstrated, named as a wing-shape TFT. Investigations of the electrical characteristics and reliabilities are supported by simulations, theoretical calculations, and structural discussions. First, through both electrical and mechanical stress simulation, the regions of degradation are confirmed to occur at the corner of the gate insulator. After long term mechanical stress, behaviors including an abnormal hump, serious threshold voltage (Vth) shifts, on-current increase, and off-current decrease are observed. By extending the active layer, also serving as a stress relief layer, removes the degradation regions away from the main channel. Therefore, the reliability of the devices is dramatically improved. The geometries of the wings in wing-shape TFTs are also in consideration. From results, with different wing lengths, a similar improvement of the reliability is shown, but the on current is enhanced when the wing length is extended. These phenomena are realized as a result of the difference in the effective width. The proposed wing-shape LTPS TFT has its potential and benefits for future flexible displays.

In this work, an opposite sub-threshold swing trend of I-curve to C-V curve in tri-layer IGZO TFT is observed. Thermal and electrical field effects during stress duration is investigated to clarify this behavior. Results indicate a carrier distribution migration phenomenon; carriers are away from the gate insulator surface after self-heating stress which is caused by defect generations at channel/GI interface. Since carrier tends to locate at the middle layer (In-rich layer) after self-heating stress, carriers away from surface defects leads to a better subthreshold swing in I-V curve. However, C-V curves detects the information of defects leading to S.S degradation.

Resistive random-access memory (RRAM) structured in crossbar arrays typically use selectors to improve noise margins by suppressing sneak path currents and leakages. Without selectors, crossbar array dimensions would be prohibitively small for practical use in storage-class memory (SCM), and compute-in-memory (CIM) applications. Most one-selector one-resistor (1S1R) memory cells fabricate the selector and RRAM independently. Here, an extremely simple process is presented to construct a 1S1R cell consisting of a metal-insulator-metal (MIM) structure of V/ITO(O2)/TiN, where the unique electrical properties of vanadium form a built-in selector. High vertical stacking density is achieved by removing the need for a separate series-connected selector. Threshold switching (TS) based on metal-insulator transition (MIT) in the vanadium top electrode (TE) selector is observed with a subthreshold swing of under 30 mV/dec. The selector is directly integrated with indium tin oxide (ITO) which provides low-voltage/high-speed resistive switching behavior (set process of

In this work, degradation due to carrier injection at the etch-stop layer was observed under dynamic switching. A significant threshold voltage shift is observed in alternating current stress but is absent in direct current stress. A model which transitions from the accumulation to depletion phases indicates electron-trapping at the etch-stop layer since the transition time is insufficient for carriers to drift back to the source/drain electrodes. Results are discussed through both horizontal and lateral band diagrams to confirm back channel injections. Also, comparing transfer curves with capacitance-voltage curves at the same threshold voltage in different structure devices provides direct evidence of electron-trapping regions. Finally, COMSOL simulation is performed to confirm the difference in electron-trapping between back channel and corner regions, a difference which leads to an abnormal hump during capacitance-voltage measurements.

Degradation in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (S.S.) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in S.S. values which appears in hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.

In today's society, displays are indispensable for digital interaction and personal contact. Therefore, the development of displays is an urgent need for the next generation. Leading the commercialization trends is the development of industrial, high-resolution, portable, and multifunctional displays. Moreover, for small-size portable displays, the most critical factor affecting future applications is their flexibility. Among the various materials that can act as the channel layer, low-temperature polycrystalline silicon (LTPS) is a potential candidate for next-generation portable displays, which require high resolution and stable reliability, and which can achieve virtual reality applications. This article is a review of the development of the LTPS thin-film transistors (TFTs) on soft and flexible electronics, especially the effect of mechanical strain. This article starts by providing an overview of the difficulties in fabricating LTPS TFTs on flexible substrates. The physical mechanism corresponding to each degradation caused by mechanical stress is presented next. Finally, to support the development of the flexible technologies and realize their commercialization, methods to overcome these mechanical strain-induced degradations are reported in three different aspects by understanding the physical degradation model. Keywords: Flexible LTPS TFT, Mechanical stress, Active layer design and mechanical absorption layer, Gate insulator quality improvement

This work compares dual gate and single gate a-InGaZnO thin film transistor devices under single gate operations. In both devices, an abnormal drain current increase in the dual gate structures was observed. The results of structural geometry experiments, Technology Computer-Aided Design, and theoretical calculations matching the experimental results provide evidence for a larger voltage potential distribution located near the top gate even when the top gate is floating. Since an additional voltage is formed near the top gate, a better gate control capability will lead to more inverted carriers. Therefore, these dual gate structures have a larger drain current than does the single gate. Finally, both positive bias stress and negative bias illumination stress in both structures are discussed. The results of positive bias stress have shown good quality of the gate insulator layer and negative bias illumination stress was discussed to confirm the coupled voltage.This work compares dual gate and single gate a-InGaZnO thin film transistor devices under single gate operations. In both devices, an abnormal drain current increase in the dual gate structures was observed. The results of structural geometry experiments, Technology Computer-Aided Design, and theoretical calculations matching the experimental results provide evidence for a larger voltage potential distribution located near the top gate even when the top gate is floating. Since an additional voltage is formed near the top gate, a better gate control capability will lead to more inverted carriers. Therefore, these dual gate structures have a larger drain current than does the single gate. Finally, both positive bias stress and negative bias illumination stress in both structures are discussed. The results of positive bias stress have shown good quality of the gate insulator layer and negative bias illumination stress was discussed to confirm the coupled voltage.

In this work, we proposed a full-color reflector using three stacked red (R), green (G), and blue (B) reflection gratings which are combined with the tunable 90° twisted nematic liquid crystals (TNLCs). The color reflector based on guided-mode resonance (GMR) gratings reflects strongly at the resonance wavelength. The optical reflectivity of GMR gratings can then be controlled by using 90° TNLCs to change the polarization of incident light. The optical characteristics and the chromaticity of the designed reflectors were evaluated by simulation. An individual RGB chip with/without LC was demonstrated experimentally. The fabricated GMR reflector for red exhibits a high TE/TM polarization ratio of >10:1 and 80% optical reflectivity at resonant wavelength, while the GMR reflector for blue only allows 60% optical reflectivity and a degraded polarization ratio of 3:1 mainly due to high optical absorption of silicon. Nevertheless, the silicon-based GMR reflector enables a wide reflection bandwidth, so a full-color reflector can be realized by vertically stacking RGB tunable reflectors. The proposed full-color reflector therefore exhibits a wide-gamut color space with low driving voltage of