Search

Although trench gate and super-junction technology have micro-trench problems when applied to the SiC process due to the material characteristics. In this paper, area effects are analyzed from the test element group with various patterns and optical proximity correction (OPC) methods are proposed and analyzed to reduce micro-trenches in the SiC trench etching process. First, the loading effects were analyzed from pattern samples with various trench widths (Wt). From experiments, the area must limited under a proper size for a uniform etching profile and reduced micro-trenches because a wider area accelerates the etch rate. Second, the area effects were more severely unbalanced at corner patterns because the corner pattern necessarily has an in-corner and out-corner that have different etching areas to each other. We can balance areas using OPC patterns to overcome this. Experiments with OPC represented improved micro-trench profile from when comparing differences of trench depth (Δdt) at out corner and in corner. As a result, the area effects can be used to improve the trench profile with optimized etching process conditions. Therefore, the trench gate and super-junction pillar of the SiC power MOSFET can have an improved uniform profile without micro-trenches using proper design and OPC.

We developed bottom-gate poly-Si TFTs (BGPs) using ELA for high resolution AMOLED. The BGPs based on our novel process to solve the disconnection of poly-Si during ELA crystallization have better reliability characteristics such as breakdown voltage (BV) and kink effect compared with the conventional top-gate poly-Si TFTs.

To improve the high resistance and low breakdown voltage (BV) of a 4H-SiC Schottky barrier diode (SBD), the metal annealing process is conventionally used; this process stabilizes the Schottky barrier height (SBH). In this paper, we apply a post-metal annealing process to 4H-SiC Ti-SBD chips and verify the effect of the changes on electrical characteristics based on the post-annealing process. The results of experiments show that the condition of 873K/30min annealing created a stable SBH and a low value of on-resistance (Ron), which improved inhomogeneity. Based on the results of EDX and TEM analysis, the cause of improved SBH at the condition of 30min was attributed to the generation of TiSix (which has a higher SBH than Ti). On the other hand, the improved value of Ron at the condition of 30min was attributed to the change to γ-phase Ti3Al (which has a low resistance because diffused Al is present) caused by proper annealing. However, when more heat is applied in the cases of 773K/60min and 873K/60min, Ron increased and the SBH decreased. The results of EDX and TEM analysis showed that the low SBH was caused by Al spiking, which created an Al Schottky junction with a lower SBH than that of the Ti Schottky junction. Higher Ron resulted from the change to α-TiAl phase at the Al-Ti interface layer because of excessive diffusion of Ti and Al, which is due to the overly applied heat.From the results produced by this work, we can enhance the Al-Ti 4H-SiC SBD electrical characteristics by applying a suitable post-annealing process. Display Omitted

We propose an analog front-end integrated circuit (IC) design for a readout IC (ROIC), which applies a fixed-voltage-bias sensing method with a capacitance transimpedance amplifier (CTIA) to an input stage in order to simplify the circuit structure of the ROIC and the IR sensor characteristic control. For a sample-and-hold stage, in order to display and control a signal detected by the IR sensor using a 2-D focal plane array, a differential delta sampling circuit is proposed, which effectively removes the fixed pattern noise. In addition, a two-stage variable-gain amplifier equipped with a rail-to-rail fully differential operational amplifier is applied to the ROIC to achieve high voltage sensitivity. The output characteristic of the proposed device is 30.84 mV/K and the linearity error rate is less than 0.07%. After checking the performance of the ROIC using an HSPICE simulation, the chip is manufactured and measured using the United Microelectronics Corporation Japan 0.35- $\mu\mbox{m}$ standard CMOS process to confirm that the simulation results from the actual design are in close agreement with the measurement results.

To improve the high resistance and low Breakdown Voltage (BV) of 4H-SiC SBD, the metal annealing process is usually used to to stabilize SBH. We confirmed that post metal annealing after the chip process also stabilizes SBH by the post annealing experiment of applying failure chips (4H-SiC Ti/Al SBD) that have a forward current (IF) under 1 [A] with high resistance, because of the metal annealing process error. The result of experiments showed that the IFincrement and BV decrement are proportional to the applied temperatures over 450 °C, and the second additional post annealing shows a decrease of IFand BV. Aluminum and Titanium transformation with post metal annealing made a decrease of SBH, so that the on-resistance is decreased and BV is decreased (in severe cases, the intense post annealing generates Aluminum spiking). From a result of this work, using a suitable post metal annealing, we can improve the IFof SiC SBD with a high resistance failure from the metal process event.

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance [1]. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don’t have a great effect on temperature change.

In Super Junction (SJ) MOSFETs, charge balance is the most important issue of the SJ fabrication process. In order to achieve the best electrical characteristics, such as breakdown voltage and on-resistance, the N-type and P-type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, which is known as the charge balance condition. In conventional charge balance analysis, based on multi-epi process SJ MOSFETs, analytical model has only N, P pillar width and doping concentration parameter. But applying a conventional charge balance principle to trench filling process, easier than Multi-epi process, is impossible due to the missing of the trench angle parameter. To achieve much more superior characteristics of on-resistance in trench filling SJ MOFET, the appropriate trench angle is necessary. So in this paper, modulated charge balance analysis is proposed, in which a trench angle parameter is added. The proposed method is validated using the TCAD simulation tool.

One of the candidate materials for phase-change memory, In3Sb1Te2 (IST), shows multilevel phase transformations from amorphous to several crystalline materials of IST, intermediate phases such as InSb, SbTe and InTe. However, its volume can change abruptly in the multilevel phase transformation, and this change can lead to vacancy movement and atomic migration, which are related to failures and reliability issues. We propose the carbon-incorporated In3Sb1Te2 (IST-C) alloy, which has higher retention ability than the IST ternary alloy. Carbon atoms delay crystallization and prevent volume change during the set/reset operation. The carbon concen- tration is 12.5%, and the activation energy increases from 5.1 eV to 5.4 eV. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Insulated Gate Bipolar Transistors(IGBTs) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the onstate voltage drop should be lowered and the switching time should be shortened. However, there is trade-off between the breakdown voltage and the on-state voltage drop. The FLoatingIsland(FLI) structure can lower the on-state voltage drop without reducing breakdown voltage. In this paper, The FLI IGBT shows an on-state voltage drop that is 22.5% lower than the conventional IGBT, even though the breakdown voltages of each IGBT are almost identical.

In this paper, fabricated by MEMS uncooled micro-bolometer detector for the study in the infrared sensitivity enhancement. Absorption layer SiOx-Metal series MDTF (metal-dielectric thin film) by high absorption rate and has a high thermal coefficient of resistance, low noise characteristics were implemented. Then MDTF were made in a vacuum deposition method. And MDTF for the analysis of the physical properties of silicon wafers were fabricated, TCR (temperature coefficient of resistance) value was made in order to measure the glass wafer and FT-IR (Fourier Transform Infrared spectroscopy) values were made in order to measure the germanium window. The analyzed results of MDTF -3 [%/K] has more characteristics of the TCR. And 8~12 um wavelength region close to 70% in the absorption characteristic.

Protected Circuit Module protects battery from over-charge and over-discharge, also prevents accidental explosion. Therefore, power MOSFET is essential to operate as a switch within the module. To reduce power loss of MOSFET, the on state voltage drop should be lowered and the switching time should be shorted. However there is trade-off between the breakdown voltage and the on state voltage drop. The TDMOS can reduce the on state voltage drop. In this paper, effect of design parameter variation on electrical properties of TDMOS, were analyzed by computer simulation. According to the analyzed results, the optimization was performed to get 65% higher breakdown voltage and 17.4% on resistance enhancement.

IGBT (insulated gate bipolar transistor) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the on state voltage drop should be lowered and the switching time should be shorted. However, there is Trade-off between the breakdown voltage and the on state voltage drop. To achieving good electrical characteristics, field stop IGBT (FS IGBT) is proposed. In this paper, 1,200 V planar gate non punch-through IGBT (planar gate NPT IGBT), planar gate FS IGBT and trench gate FS IGBT is designed and optimized. The simulation results are compared with each three structures. In results, we optain optimal design parameters and confirm excellence of trench gate FS IGBT. Experimental result by using medici, shows 40% improvement of on state voltage drop.

Department of Electrical Engineering, Korea University, Seoul 136-701, Korea(Received March 16, 2012; Revised March 21, 2012; Accepted March 22, 2012)Abstract: IGBT (insulated gate bipolar transistor) has been widely used around the power industry as it has good switching performance and its excellent conductance. In order to reduce power loss during switch turn-on state, it is essential to reduce its resistance. However, trade off relationship between breakdown voltage and device conductance is the greatest obstacle on the way of improvement. Floating island structure is one of the solutions. Still, under optimized device condition for the best performance, improvement rate is negligible. Therefore, this paper suggests adding trench gate on floating island structure to eliminate JFET (junction field effect transistor) area to reduce resistance and activate floating island effect. Experimental result by 2D simulation using TCAD, shows 20% improvement of turn-on state voltage drop.Keywords: Floating island, Trench gate, IGBT, Power semiconductor device

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 ㎷/℃, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 ㎛ standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

A uncooled infrared ray sensor used in an infrared thermal imaging detector has many advantages. But because the uncooled infrared ray sensor is made by MEMS (micro-electro-mechanical system) process variation of offset is large. In this paper, to solve process variation of offset a ROIC for uncooled infrared ray sensor that has process variation of offset compensation technique using differential delta sampling and reference signal compensation circuit was proposed. As a result of simulation that uses the proposed ROIC, it was possible to acquire compensated output characteristics without process variation of offsets.

The proposed UHF Gen2 RFID chip expands its applications to both FFC and NFC through dual field communication scheme with the dual antenna ports. An RF front end circuit with dual field communication antenna ports and the embedded FeRAM technology on the passive UHF Gen2 RFID chip enables the excellent operating performances and the low cost chip for the tag chip applications from the item level to pallet. The metal-ferroelectric-metal (MFM) capacitor, which is the replacement capacitor device for metal-insulator-metal (MIM) or poly-insulator-poly (PIP), is composed of the ferroelectric material as a dielectric insulator. The MFM capacitor is made simultaneously during the FeRAM memory cell process integration without any additional process integration cost. The MFM capacitor of PZT with the thickness of 0.15μm has the high capacitance value of 20–40 fF at unit μm2 area size. The MFM can be stacked over the CMOS layout area, which saves dramatically the capacitor layout area. The MFM capacitor also has th...

Three-dimensional (3D) dynamic random-access memory (DRAM) with TSVs has been proposed due to continuous demands for low-power and high-density memory without IO loading limitation. However, the process difference among the stacked dies causes the timing mismatch of internal signals. To remove signal confliction and reduce signal skews among the stacked dies, the simultaneous process self-calibration scheme is proposed. The stacked dies using the proposed scheme detect the slowest signal among the stacked dies and internal signals are aligned with the slowest signal at the same time. The time for aligned operation is within one read loop and the scheme is turned off after calibration to reduce additional standby current. The 3D double-data rate 4 (DDR4) DRAM using the proposed scheme is operated over 2133 Mbit/s at 1.2 V.

A novel wide angle and variable-focus imaging module based on a miniaturized liquid lens is presented for capsule endoscopy applications. For these applications, it is desirable to have features such as a wide field of view (FOV), variable focus, small size, and low power consumption, thereby taking full advantage of the miniaturized liquid lens. The proposed imaging module has three aspheric plastic lenses for a wide FOV, and one liquid lens that can change the focal length by as much as 24.5 cm with a bias voltage difference of 23 Vrms for variable focusing. The assembled lens module has an overall length of 8.4 mm and a FOV of 120.5°. The realized imaging module including the proposed lenses is small enough to be inserted into a capsule endoscope, and it is expected to improve the diagnostic capability of capsule endoscopes.

Gallium nitride (GaN), wide bandgap semiconductor, has attracted much attention because they are projected to have much better performance than silicon. In this paper, effects of design parameters change of GaN power static induction transistor (SIT) on the electrical characteristics (breakdown voltage, on resistance) were analyzed by computer simulation. According to the analyzed results, the optimization was performed to get power GaN SIT that has 600 V class breakdown voltage. As a result, we could get optimized 600 V class power GaN SIT that has higher breakdown voltage and lower On resistance with a thin (a several micro-meters) thickness of the channel layer.

The maximum peak-to-peak radio frequency (RF) signal antenna voltage level can be extended to reach to over 12 Vpp, −6 V to +6 V. Thus it is desirable that the electro-static discharge (ESD) device does not turn on at the normal operating RF antenna signal voltage level. The turn-on threshold negative voltage of the ESD device of the PN diode type is around −0.5 V in the conventional radio frequency identification (RFID) chip. The asymmetric threshold voltage characteristics of the ESD device of the RFID chip makes the distortion of the RF antenna signal at the high intensity RF input field. In the proposed floating base vertical PNP ESD device, N-type doped N-WELL floating base is sandwiched between two p-type P+ emitter and P-WELL collector. Floating base BJT ESD device enhances the performance of parasitic BJT current in the ESD mode. During the negative voltage phase of RF antenna input signal, the negative voltage of RF antenna input is extended to around −10 V. This extension of RF antenna ...

" # $%& '( )* % +&&,( ! )-. % +&&,- . )-. +&& /&' ( )# $ 0. ) 0 1# !2 ! ) ) . 0 3 )#! 2 $) 0 ! ) ! 0# 45" ) ! 2 2 # )6 )# 0. ) 6 6 7 . 6 " 6 6 )4 !# !! 2 .$ 8# 2 )# 0. )8# )$ 0. ! "+&9 ! 6 7) 2 0. ! 2 )$ !4 6 ! ") # 45# ) ) 2 )# $ 0. !!# . !! ) 6 7) 2 ) !#0 ! 0 ) : ! ) ! 0# ! !2 !1# "! ! 0 ! #! !4)" (; 2 ) ) 0 )

A bolometer sensor used in an infrared thermal imaging system has many advantages on the process because it does not need a separate cooling system and its manufacturing is easy. However the sensitivity of the bolometer is low and the fixed pattern noise(FPN) is large, because the bolometer sensor is made by micro electro mechanical systems (MEMS). These problems can be fixed-by using the high performance readout integrated circuit(ROIC) with noise reduction techniques. In this paper, we propose differential delta sampling circuit to remove the mismatch noise of ROIC itself, the FPN of the bolometer. And for reduction of FPN noise, the reference signal compensation circuit which compensate the reference signal by using on-resistance of MOS transistor was proposed.

In this paper, high performance read-out integrated circuits (ROIC) for infrared (IR) image sensor applications is proposed. Because an uncooled microbolometer image sensor, used in an IR image sensor, is made by a micro electro mechanical systems process, the resistance of bolometer by each process does not appear same value under same temperature condition. This resistance variation generates a different output signal for same input by each chip. In order to improve on these drawbacks, a ROIC, which compensates for the error described above, was designed. Instead of a single input mode, a differential input mode ROIC was proposed and thus, a new circuit structure was proposed. Using results from a computer simulation, improvements such as that the effect of the process error was decreased 10---12% without an additional compensation circuit was found. Based on the simulation results, a prototype device including a ROIC and a micro bolometer with 16 × 16 cell arrays was fabricated and characterized.

N-WELL floating base is sandwiched between P+ emitter and P-WELL collector in the proposed floating base vertical PNP electro-static discharge (ESD) protection device. Floating base bipolar junction transistor (BJT) ESD protection device increases the current performance of the parasitic BJT in the ESD mode. During the negative voltage phase of RF antenna signal, the negative voltage range of RF antenna signal is extended to around −10 V at the high RF power field without latch-up failure. The minimum P+ anode layout area of the floating base type BJT ESD device is 400 μm2 for the target ESD voltage of 2000 V in human body model (HBM) mode. The parasitic capacitance of the floating base type BJT ESD protection device is about 0.4 pF. The layout area of the proposed floating base type BJT ESD protection device is 50% smaller that of the conventional NMOS diode type ESD protection device for the target ESD voltage of 2000 V in HBM mode. The rewards of the floating base type BJT ESD device will come...

As infrared light radiates, the CMOS Readout IC (ROIC) for the microbolometer typed infrared sensor detects voltage or current which is caused by the variation of resistance in the bolometer sensor. A serious problem we may have in designing the ROIC is the value of bolometer and reference resistors will be changed due to process variation. Since each pixel does not have the same value of resistance, fixed pattern noise problems happen during the sensor operations. In this paper, we propose a novel technique to compensate the fluctuation of reference resistance with taking account of process variation. By using a comparator and a cross coupled latch, we will make the value of reference resistor same as the bolometer`s.

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration , size of with , and off-state leakage current below . We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

The metal-ferroelectric-metal (MFM) capacitor in ferroelectric random access memory (FeRAM) security embedded RFID chip is used not only in the memory cell region but also used in the analog and digital circuit area for low cost capacitance device and high security algorithm. MFM based security FeRAM braces for a wide range of security threats such as reverse engineering, cloning, and tampering. High security performance solution of on-chip FeRAM based register key is implemented to prepare against security attacking. RF transferring sensitivity properties with MFM capacitor are almost same or better than that with poly-insulator-poly (PIP) capacitor and metal-insulator-metal (MIM), and MOS capacitor. The measured power consumption of FeRAM embedded RFID chip without crypto processor engine is about 10μ W with the write sensitivity of -18dBm.

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

The conventional IGBT has two problems to make the device taking high performance. The one is high on state voltage drop associated with JFET region, the other is low breakdown voltage associated with concentrating the electric field on the junction of between p base and n drift. This paper is about the structure to effectively improve both the lower on state voltage drop and the higher breakdown voltage than the conventional IGBT. For the fabrication of the circular trench IGBT with the circular trench layer, it is necessary to perform the only one wet oxidation step for the circular trench layer. Analysis on both the on state voltage drop and the breakdown voltage show the improved values compared to the conventional IGBT structure. Because the circular trench layer disperses electric field from the junction of between p base and n drift to circular trench, the breakdown voltage increase. The on state voltage drop decrease due to reduction of JFET region and direction changed of current path which pass through reversed layer channel. The electrical characteristics were studied by MEDICI simulation results.

It is very important to observe the change in the atomic structure of melt-quenched amorphous Ge2Sb2Te5 (GST) to discover the failure mechanism of phase-change random access memory (PRAM) devices during the reset process. We fabricated the phase-change devices and measured the initial resistance changes with various reset pulse amplitudes. For the observation of the atomic structure changes of GST thin films, we designed the specimens for transmission electron microscopy (TEM) and annealed them below and above the melting temperature of GST (Tm = 650 °C) before quenching. The annealed-and-quenched GST at 630 °C has a hexagonal structure with a grain size of about 10 nm after the partial melting. The annealed-and-quenched GST at 750 °C also has a hexagonal structure because of the latent heat. The observed atomic structures of GST are in accordance with the resistance changes inferred from the fabricated edge-contact type of PRAM cell. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)