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The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized in upcoming high-performance hardware SNN systems.

In this work, we developed a SPICE compact model of a dual-gate positive-feedback field-effect transistor (FBFET) for circuit simulations by fitting the model to measurement results. We fabricated a FBFET and investigated the DC and transient characteristics. The fabricated FBFET has an extremely low sub-threshold slope and a low off current. The FBFET operates as a forward-biased PN diode after the device is turned on due to the positive feedback loop between the integrated charges and the potential barrier. When enough electrons are accumulated in the floating body, the potential barrier is lowered and the FBFET is turned on rapidly, and due to the integrated charges, the FBFET has memory characteristics which approximate hose of 1T-DRAM. Reflecting these electrical characteristics of the FBFET, we undertook SPICE modeling and obtained simulation results that were similar to the measurement characteristics. Finally, we implement a modified inverter with the FBFET connected in parallel with an n -type MOSFET (NMOS). Due to the superior sub-threshold characteristics of the FBFET, it effectively suppresses the sub-threshold currents.

In this paper, we proposed and fabricated a polysilicon-based four-terminal synaptic transistor. The device has an asymmetric dual-gate structure. The top gate, which uses a thin SiO₂ layer as the gate dielectric, is the input terminal of the synaptic transistor, which receives spikes from pre-synaptic neurons. Meanwhile, a nitride trapping layer was inserted between the channel and the bottom gate to serve as a non-volatile memory. The bottom gate is the node that receives the post-neuron feedback signals and adjusts the synaptic weight. With this double-gate structure, the proposed artificial synapse can perform short-/long-term memory operations. In addition to the basic unit cell characteristics, a highly integrated synapse array structure is also proposed. In our array structure, the top gate is tied in the word-line direction to accept the input signal. Drain contacts are also tied in the same direction. With regard to bit-line direction, the source terminals are tied to carry post-synaptic signals and the bottom gate line receives feedback signals from the post-synaptic neurons.

In this paper, we analyze hot carrier injection (HCI) in an asymmetric dual gate structure with a charge storage layer. In a floating gate device, holes injected by HCI can move freely in the valence band, since the channel potential is constant. In case of charge trapping layer, however, holes are trapped only in the drain side where impact ionization occurs. Therefore, only small threshold voltage shift occurs because channel formation is enhanced only in the drain side. When the gate length is under 100 nm, trapped holes in the drain side start to control the whole channel. Thus, we expect that HCI into the charge trapping layer can be used as a non-volatile memory (NVM) mechanism in short channel devices.

In this paper, we investigated the dependence of minority carrier lifetime on dual gate FBFET. Generally, depending on the channel condition or trap density, the lifetime of minority carrier can be degraded. Since the potential barrier lowering through the accumulated carriers is essential for positive feedback, the deterioration of lifetime can make a critical influence on the operation of device. Therefore, we verified the tendency of threshold voltage according to carrier lifetime and channel length. Through the comparison with p-n diode and FBFET, we drew the relation between lifetime and threshold voltage. As a result, it has been confirmed that the device with significantly deteriorated lifetime or the device with extremely long channel does not effectively generate feedback and loses its steep switching characteristics.

In this study, we proposed an online learning method using spike-timing dependent plasticity (STDP) whose operation is analogous to gradient descent, the most successful learning algorithm for nonspiking artificial neural networks (ANNs). With a model of a 4-terminal synaptic transistor we previously reported, a single-layer neural network implemented on the cross-point array was simulated by MATLAB to train binary MNIST samples with gradient descent algorithm. In addition, a proposed pulse scheme based on STDP was used to train the same network by applying teaching pulses having positive and negative timing differences with respect to input pulses to the back gate of the synaptic transistors. By comparing the extracted synaptic weight maps from both methods, therefore, the network trained by gradient descent was almost equally reproduced by the proposed method which was performed fully on hardware without computer calculation.

We studied the pseudo-homeothermic synaptic behaviors by integrating complimentary metal-oxide-semiconductor-compatible materials (hafnium oxide, aluminum oxide, and silicon substrate). A wide range of temperatures, from 25 °C up to 145 °C, in neuronal dynamics was achieved owing to the homeothermic properties and the possibility of spike-induced synaptic behaviors was demonstrated, both presenting critical milestones for the use of emerging memristor-type neuromorphic computing systems in the near future. Biological synaptic behaviors, such as long-term potentiation, long-term depression, and spike-timing-dependent plasticity, are developed systematically, and comprehensive neural network analysis is used for temperature changes and to conform spike-induced neuronal dynamics, providing a new research regime of neurocomputing for potentially harsh environments to overcome the self-heating issue in neuromorphic chips.

We designed the CMOS analog integrate and fire (I&F) neuron circuit can drive resistive synaptic device. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, asymmetric negative and positive pulse generation part, a refractory part, and finally a back-propagation pulse generation part for learning of the synaptic devices. The resistive synaptic devices were fabricated using HfOx switching layer by atomic layer deposition (ALD). The resistive synaptic device had gradual set and reset characteristics and the conductance was adjusted by spike-timing-dependent-plasticity (STDP) learning rule. We carried out circuit simulation of synaptic device and CMOS neuron circuit. And we have developed an unsupervised spiking neural networks (SNNs) for 5 × 5 pattern recognition and classification using the neuron circuit and synaptic devices. The hardware-based SNNs can autonomously and efficiently control the weight updates of the synapses between neurons, without the aid of software calculations.

Tunneling field-effect transistors (TFETs) have been studied as a candidate for low-power device due to the remarkable subthreshold characteristics. However, digital circuits composed of TFET have significantly large propagation delay compared with the conventional MOSFET circuits because of small current drivability and large gate-to-drain capacitance. In this work, the electrical characteristics of the self-boosted TFETs with nitride charge trapping layer have been studied using TCAD simulations. Trapped charges in the nitride layer improve subthreshold characteristics and on-current (I(ON)) of both nTFET and pTFET during gate bias sweep. In addition, the benefits of the self-boosted TFET devices to low supply voltage system application are investigated. Energy consumption and propagation delay of both conventional and self-boosted TFET inverters are compared by the mixed-mode circuit simulation study. Energy consumption is almost same but the propagation delay of the self-boosted TFET inverter is reduced especially for ultra-low voltage operation where system delay is increased dramatically.

We developed an analog neuron circuit that can work with Si-based synaptic devices. N-channel and p-channel synaptic devices connected to current mirrors constitute the synaptic connection and integration parts to implement the excitation and inhibition mechanisms of biological neurons. The normal inverter controlling delay time and the modified inverter making negative pulse constitute the action-potential generation part to generate output action-potential. Connecting output potential to the synaptic device, we implement the spike-timing-dependent-plasticity (STDP) mechanism, adjusting the conductance of synapse. As we have constituted the analog neuron circuit using 4-terminal synaptic device without additional switch and logic operation, we can emulate the operation of the neuron with minimum number of devices and power dissipation.

A three-directional motion-compensation mask-based novel look-up table method is proposed and implemented on graphics processing units (GPUs) for video-rate generation of digital holographic videos of three-dimensional (3D) scenes. Since the proposed method is designed to be well matched with the software and memory structures of GPUs, the number of compute-unified-device-architecture kernel function calls can be significantly reduced. This results in a great increase of the computational speed of the proposed method, allowing video-rate generation of the computer-generated hologram (CGH) patterns of 3D scenes. Experimental results reveal that the proposed method can generate 39.8 frames of Fresnel CGH patterns with 1920×1080 pixels per second for the test 3D video scenario with 12,088 object points on dual GPU boards of NVIDIA GTX TITANs, and they confirm the feasibility of the proposed method in the practical application fields of electroholographic 3D displays.

A new object tracking mask-based novel-look-up-table (OTM-NLUT) method is proposed and implemented on graphics-processing-units (GPUs) for real-time generation of holographic videos of three-dimensional (3-D) scenes. Since the proposed method is designed to be matched with software and memory structures of the GPU, the number of compute-unified-device-architecture (CUDA) kernel function calls and the computer-generated hologram (CGH) buffer size of the proposed method have been significantly reduced. It therefore results in a great increase of the computational speed of the proposed method and enables real-time generation of CGH patterns of 3-D scenes. Experimental results show that the proposed method can generate 31.1 frames of Fresnel CGH patterns with 1,920 × 1,080 pixels per second, on average, for three test 3-D video scenarios with 12,666 object points on three GPU boards of NVIDIA GTX TITAN, and confirm the feasibility of the proposed method in the practical application of electro-holographic 3-D displays.

A novel approach for fast generation of video holograms of three-dimensional (3-D) moving objects using a motion compensation-based novel-look-up-table (MC-N-LUT) method is proposed. Motion compensation has been widely employed in compression of conventional 2-D video data because of its ability to exploit high temporal correlation between successive video frames. Here, this concept of motion-compensation is firstly applied to the N-LUT based on its inherent property of shift-invariance. That is, motion vectors of 3-D moving objects are extracted between the two consecutive video frames, and with them motions of the 3-D objects at each frame are compensated. Then, through this process, 3-D object data to be calculated for its video holograms are massively reduced, which results in a dramatic increase of the computational speed of the proposed method. Experimental results with three kinds of 3-D video scenarios reveal that the average number of calculated object points and the average calculation time for one object point of the proposed method, have found to be reduced down to 86.95%, 86.53% and 34.99%, 32.30%, respectively compared to those of the conventional N-LUT and temporal redundancy-based N-LUT (TR-N-LUT) methods.

Objectives: To explore how the expression of emotional support in an online breast cancer support group changes over time, and what factors predict this pattern of change., Methods: We conducted growth curve modeling with data collected from 192 participants in an online breast cancer support group within the Comprehensive Health Enhancement Support System (CHESS) during a 24-week intervention period., Results: Individual expression of emotional support tends to increase over time for the first 12 weeks of the intervention, but then decrease slightly with time after that. In addition, we found that age, living situation, comfort level with computer and the Internet, coping strategies were important factors in predicting the changing pattern of expressing emotional support., Conclusions: Expressing emotional support changed in a quadratic trajectory, with a range of factors predicting the changing pattern of expression., Practical Implications: These results can provide important information for e-health researchers and physicians in determining the benefits individuals can gain from participation in should CMSS groups as the purpose of cancer treatment., (Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.)

Gammi-danguieumja (GD) is clinically used in South Korea for treating atopic dermatitis. However, its effects in experimental models remain unknown. We investigated a possible effect of GD on cytokines production using human T cell line (MOLT-4) or human mast cell line. As a result, GD (0.01 mg/mL)-containing medium in stimulated culture supernatants increased IL-2 and IFN-gamma, and decreased IL-4 secretion in MOLT-4. GD (0.01-1 mg/mL)-containing medium in stimulated culture supernatants dose-dependently and significantly decreased IL-8, IL-13, and tumor necrosis factor-alpha secretion on the phorbol 12-myristate 13-acetate and A23187-stimulated HMC-1. In addition, GD inhibited histamine release from activated mast cells. These results suggest that GD contributes to the regulation of atopic allergic reactions.