Search

In this paper, we propose a new search algorithm that reduces the memory bandwidth required for finding active edges in OpenVG rendering. It simultaneously prepares an active edge table for each scanline so that one edge may be stored in several active edge tables, which depends on the lifetime of each edge. It also gives us another benefit so that we can implement the multiple scanline filling in parallel for performance improvement. Experimental results show the external memory accesses of the proposed algorithm can be substantially reduced and the performance of the proposed dual-scanline filling rendering architecture can be significantly increased, especially for high-quality images. We implemented an OpenVG accelerator using the dual-scanline filling rendering with one-poly four-metal 0.18-mum CMOS technology, which requires about 350 K gates and operates at 100 MHz.

We propose an optimized scanline filling algorithm for OpenVGtwo-dimensional vector graphics. For each scanline of a path, it adaptively selects a left or right scanning direction that minimizes the number of pixels visited during scanning. According to the experimental results, the proposed algorithm reduces the number of pixels visited by 6 to 37% relative to that with a constant scanning direction for all the scanlines.

A multi-core platform for high-performance video applications is proposed that contains multiple RISC clusters. Each cluster, which contains up to four cores and exploits thread-level parallelism, is allocated for a function block and connected to other clusters through two communication networks: one for control transfer and the other for data transfer. As an example, several mapping results of the H.264/AVC high profile 720p decoder to the proposed platform are presented. According to the experimental results, we found that this platform is suitable for implementing a multi-standard video codec.

An optimized rendering algorithm of the OpenVG 2D vector graphics for hardware implementation is presented in this paper. In the rendering algorithm we adopted a hybrid of raster and vector rendering, which uses vector rendering only within each scanline, to reduce both the number of external memory accesses and the computational complexity. We implemented a hardware accelerator with the proposed algorithm. Experimental results show that our hardware accelerator can handle 11.8 fps of Tiger image for a QVGA panel at the operating clock frequency of 100 MHz.