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In this paper, a hybrid uniplanar compact electromagnetic bandgap (UC-EBG) design is proposed with a wide-band noise suppression in power planes of printed circuit boards (PCBs). To achieve wide-band noise suppression, the proposed hybrid UC-EBG design employs a combination of various uniplanar EBG unit cells with different sizes which have different frequency ranges of noise suppression corresponding to the size of the cells. In addition, an analytic model of the EBG unit cell composed of cavity resonant model and meander line inductance is proposed and validated by 3-dimensional field simulation and measurement. To demonstrate the proposed design, a heterogeneous group of unit cells with different sizes was selected and the noise transfer function was compared with that of a conventional UC-EBG structure. The proposed hybrid UC-EBG design is experimentally verified by noise transfer function measurement with a significant expansion of the stopband up to 478 % in comparison to the conventional uniplanar EBG designs with the same area occupation.

This paper presents the modeling of bifurcation phenomena in a wireless power transfer (WPT) system along with its application in the testing of conducted susceptibility (CS). The presented model represents an analytic transfer function based on the equivalent circuit models of strongly coupled coils, and its validation was performed using a simple WPT system designed and fabricated as equipment under test (EUT). Additionally, experimental verification of effectiveness of the presented model was performed via transfer-function measurement. The presented model was applied to estimate the impact of conducted noise on measurement-based CS testing of WPT systems demonstrating bifurcation phenomena. Results obtained in this investigation demonstrate that the impact of conducted noise with bifurcation phenomena can be successfully estimated using the presented model.

In this paper, a behavior modeling method of a buck converter with adaptive voltage positioning (AVP) and PCB parasitics for power distribution network design (PDN) is introduced. The behavior model of voltage regulator module (VRM) is previously proposed for the power integrity modeling and analysis. The proposed behavior model is applied to the buck VRM in a practical high-speed digital board. For the completeness of the behavior model, an AVP design and PCB parasitics are applied to reproduce the power supply rail noise in the practical design. To validate the behavior model, the design parameters of voltage and current controllers of buck VRM in the board are extracted based on the measurement. The proposed model shows a good correlation with the measurement under various loading conditions.

In this paper, the power supply noise associated with package parasitics in an on-chip low-dropout (LDO) regulator is investigated. The on-chip LDO regulator with off-chip decoupling capacitors has power supply rail noise typically in the frequency range of few hundreds of MHz, which is related to the inductive package interconnects and the parasitic capacitance of the pass transistor. An equivalent circuit is proposed to model the power supply noise and understand the effect of inductive package interconnects. Based on the proposed equivalent circuit, the mitigation of the power supply noise from a package design perspective is discussed.

In this paper, a methodology to analyze the power supply induced jitter (PSIJ) of high speed output buffer with on-die low-dropout (LDO) voltage regulator is presented. The approach relies on separate analysis of the LDO block and the buffer block. The total system level PSIJ analysis is achieved by combining the stand-alone results together. The AC analysis of power supply rejection ratio (PSRR) of LDO is performed. The loading effect of the buffer is also included. The PSIJ sensitivity analysis of the output buffer is obtained by transient analysis varying the frequency of sinusoidal power rail noise. The system PSIJ sensitivity analysis is completed by multiplying the LDO block PSRR response with the buffer block PSIJ sensitivity. This procedure allows designer to evaluate the system PSIJ with fewer and faster simulations. The contribution of different blocks can be clearly revealed. The proposed approach is validated through Hspice simulation of the entire system level circuit. Reasonably good accuracy has been achieved with the proposed analysis method.

In this paper, a dielectric properties extraction method for millimeter-wave applications is presented. Substrate integrated waveguide (SIW) cavity resonators with the same structure and varied thicknesses are employed to separate the dissipation factor (DF) of the substrate material for the cavity resonators. The dielectric constant and loss tangent of the dielectric substrate for the SIW is extracted at the resonance frequencies based on the unloaded Q-factors of transmission loss measurement. The DF from the unloaded Q-factors, which is highly dependent on the thickness of the substrate, is extracted using an iterative fitting process for the substrate thickness estimation without cross sectioning. To validate the extraction method, the SIW cavity resonators are fabricated using RO4003C substrate material and the dielectric properties are extracted in the X-band (8.2 to 12.4 GHz). The extracted thicknesses of the SIW resonators are validated by cross-sectioning. Additionally, the extracted dielectric properties are also verified by comparing the dielectric characteristics of the SIW resonators with the different thicknesses. With the presented method, the time expense for the conventional dielectric characterization method with cross-sectioning is reduced.

In this paper, a simulation-based system-level conducted susceptibility (CS) testing method for a wireless power transfer (WPT) system is proposed. The proposed method employs 3-dimensional electromagnetic (3D EM) models as well as equivalent circuit models to replace the measurement-based CS testing method based on the International Electrotechnical Commission 61000-4-6 standard. The conducted-noise source and equipment under test (EUT) are modeled in a circuit simulator. The conduction path, bulk current injection probe, and calibration jig are modeled using the 3D field simulator. A simple WPT system is designed and fabricated as the EUT for the CS test. The proposed method is successfully verified by comparing the voltage waveforms with measurement-based CS testing method. Additionally, as an application of the proposed method, a simulation-based evaluation of the conducted-noise filters is conducted. By using the proposed method, it is expected that the time and cost expense of setting up the test setup, as well as the testing procedure for the conventional measurement-based CS testing, will be drastically reduced. In addition, the proposed method can be used to estimate the conducted immunity of a system in the early stage of the design cycle prior to production.

In this paper, a simulation-based conducted susceptibility (CS) testing method for wireless power transfer (WPT) systems is presented. The presented method is meant to replace the measurement-based CS testing specified in IEC 61000-4-6 standard with circuit and 3-dimensional field simulators. The conduction noise sources, propagation path, and equipment under test are modeled by the equivalent circuit models in a circuit simulator. The calibration jig dedicated to inject the standard testing noise is modeled in a 3-dimensional field solver. A wireless power transfer (WPT) system is designed to apply the presented CS testing method. The voltage and timing noise on the transferred signals and the output DC levels at the receiver are employed as criteria in the presented simulation-based CS testing method. With the presented method, time expense for the conventional measurement-based CS testing is dramatically reduced, and the testing reliability is improved without human errors that can occur in the conventional measurement-based CS testing methodology.