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As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and applied to lithography field. And we have struggled not only to obtain sufficient process window with those techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot management. Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip. Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScopeTM, which is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150TM. In this paper, new verification methodology based on design based analysis will be introduced as an alternative method for effective control of OPC accuracy and hot spot management.

Scanner mismatch has become one of the critical issues in high volume memory production. There are several components that contribute to the scanner CD mismatch. One of the major components is illumination pupil difference between scanners. Because of acceleration of dimensional shrinking in memory devices, the CD mismatch became more critical in electrical performance and process window. In this work, we demonstrated computational lithography model based scanner matching for sub 3x nm memory devices. We used ASML XT:1900Gi as a reference scanner and ASML NXT:1950i as the to-be-matched scanner. Wafer metrology data and scanner specific parameters are used to build a computational model, and determine the optimal settings by model simulation to minimize the CD difference between scanners. Nano Geometry Research (NGR) was used as a wafer CD metrology tool for both model calibration and matching result verification. The extracted pupil parameters from measured source map from both before and after matching are inspected and analyzed. Simulated and measured process window changes by applying the matching sub-recipe are also evaluated.