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Non-invasive, closed-loop brain modulation offers an accessible and cost-effective means of evaluating and modulating one’s mental and physical well-being, such as Parkinson’s disease, epilepsy, and sleep disorders. However, wearable EEG systems pose significant challenges for the analog front-end (AFE) circuits in view of µV-level EEG signals of interest, multiple sources of interference, and ill-defined skin contact. This paper presents a direct-digitization AFE tailored for dry-electrode scalp EEG recording, characterized by wide input dynamic range (DR) and high input impedance. The AFE utilizes a second-order 5-bit delta-delta sigma (Δ-ΔΣ) ADC to shape DC electrode offset (DEO) and low-frequency disturbances while retaining high accuracy. A non-inverting pseudo-differential instrumentation amplifier (IA) embedded in the ADC ensures high input impedance (Zin) and common-mode rejection ratio (CMRR). Fabricated in a standard 0.18-μm CMOS process, the AFE delivers 700-mVpp input signal range, 95.3-dB DR, 87-dB SNDR, and 800-MΩ input impedance at 50 Hz while consuming 88.4µW from a 1.2 V supply. The benefits of high DR and high input impedance have been validated by dry-electrode EEG measurement.

This brief describes a self-zoom analog-to-digital converter (ADC), where zooming function is implemented by subtracting quantizer output with digital processing from input signal. Self-zoom employs a digital filter instead of a coarse ADC for zoom implementation, resulting in improved efficiency. In addition, this brief uses a 2.25-bit quantizer to achieve 5-bit self-zoom and utilizes a fast startup scheme to optimize the initiation speed. The prototype ADC was manufactured in $0.18~\mu \text{m}$ CMOS technology and occupies an area of 0.34 mm 2. In a 3.9 kHz bandwidth, the ADC achieves a DR of 114.5 dB, a SNDR of 108.7 dB, and consumes $385~\mu \text{W}$ under a 1.8V supply. This results in state-of-the-art power efficiency, in terms of FoMDR of 184.6 dB and FoMSNDR of 178.8 dB.

This article describes an ultra-high input-impedance active electrode (AE) circuit and the system to sense biopotential signals through a capacitively coupled interface. Various techniques from both circuit and system aspects are used to eliminate the input parasitic capacitance of the AE. On-chip parasitic capacitance is compensated by an auto-calibrated positive feedback loop (PFL) without applying any reference signal. A capacitor down-scaling technique combined with SAR-assisted PFL calibration enables femtofarad-level resolution of the capacitor array, alleviating the practical constraints of the conventional PFL to implement a small capacitor below 10 fF. Besides, a dummy input structure ensures that the pad and electrostatic discharge (ESD) capacitances are also canceled by the PFL, while off-chip parasitic capacitance on the printed circuit board (PCB) is nulled by active shielding. Fabricated in a standard 0.18- $\mu \text{m}$ 1P6M CMOS process, the AE achieves an ultra-high input impedance of 136 $\text{G}\Omega $ at 60 Hz (average of 10 samples). This is equivalent to an input capacitance of 19.5 fF and corresponds to a $2.7\times $ – $68\times $ improvement over the state-of-the-art. The AE exhibits an input signal range of 700 mVpp and an input-referred noise of $0.72 \mu \text{V}_{\mathrm {rms}}$ (0.5–100 Hz) while consuming $10.46 \mu \text{W}$ from a 1.2-V supply. Each AE integrates an IC and a 3-cm2 copper electrode on the PCB, and the wearable system prototypes successfully measured high-quality electrocardiogram (ECG) and electroencephalogram (EEG) signals from test subjects through capacitively coupled interfaces.

This article presents a fully integrated digital polar transmitter (DPTX) incorporating an efficiency-enhanced digital power amplifier (DPA) and a high-resolution digital-to-time converter (DTC). The proposed single-ended Doherty (SED) PA topology with switched-capacitor (SC) arrays can generate four power efficiency peaks that significantly improve the power-added efficiency (PAE) at the power amplifier (PA)’s power back-offs (PBOs). In addition, this work utilizes a three-segment DTC, built with a delay-locked loop (DLL), to improve the phase resolution and enable real-time process-voltage-temperature (PVT) calibration of the DTC. Fabricated in a 28 nm CMOS technology, the DPTX achieves a peak output power ( $P_{\mathrm {out}}$ ) of 27.7 dBm and a peak PAE of 33.4% at a 2.1 GHz carrier frequency. The PAEs at 2.5, 6, and 12 dB PBOs are 31.1%, 24.5%, and 18%, respectively. With the 2.1 GHz carrier, the DTC achieves 360° full output phase range, ±1.3° differential nonlinearity (DNL), ±1.7° integral nonlinearity (INL), and −133.86 dBc/Hz phase noise at a frequency offset of 1 MHz, while the power dissipation is only 14 mW. When testing the 10 MHz (and 20 MHz) long term evolution (LTE) 64 QAM signals with a 6.2 (5.0) dB peak-to-average power ratio (PAPR), the DPTX achieves an average $P_{\mathrm {out}}$ of 21.5 (22.7) dBm, an average PAE of 23.5% (24.6%), an average system efficiency (SE) of 22.5% (23.8%),–30.6 (–27.7) dB error vector magnitude (EVM), and–34.2/–32.6 (–30.1/–29.2) dBc adjacent channel leakage ratio (ACLR). Note that these results have been achieved with only the ON-chip digital pre-distortion (DPD) algorithm.

This article describes a power-efficient, high dynamic range (DR) incremental ADC (IADC) for wearable biopotential signals recording, where DC and low-frequency disturbances such as electrode offset, 50/60 Hz interference and motion artifact must be tolerated. To achieve a wide DR, the IADC performs a three-step conversion by combining zoom-SAR and extended counting (EC) on top of a second-order incremental delta-sigma modulator (ΔΣM). The hybrid architecture notably reduces the oversampling ratio (OSR) with respect to conventional incremental ΔΣMs, while using the EC further improves the Signal-to-Noise-and-Distortion Ratio (SNDR) by 7.4 to 25.6 dB. Fabricated in a 0.18-μm CMOS technology, the IADC achieves 107.6-dB DR, 104.9-dB peak SNR, and 99.3-dB peak SNDR at 2 kS/s while dissipating 130 μW from 1.8-V (analog) / 1.2-V (digital) supply. This translates to a highly competitive FoMDR of 176.5 dB. The high-DR IADC reduces the gain of the preceding instrumentation amplifier (IA) such that significant DC and low-frequency disturbances can be tolerated. The advantages of high DR have been demonstrated by wearable Electrocardiography (ECG) and Electroencephalography (EEG) recordings under motion artifact.

This brief describes a power-efficient time-domain analog front-end (AFE) for autonomous sensor nodes. This AFE combines an input pulse-width modulator (PWM) and a gated ring oscillator (GRO) to facilitate low-voltage analog building blocks. The input PWM is implemented with pseudo-differential comparators for voltage-to-time conversion, achieving high input impedance and linearity concurrently. A non-equidistant GRO works at a fixed frequency and quantizes the PWM output in time domain, realizing the first-order noise shaping. The AFE is implemented in a $0.18\mu \text{m}$ standard CMOS process. Clocked at 20kHz (500Hz bandwidth), the AFE achieves 81.6dB peak SNDR, $540{\mathrm{ mV}}_{\mathrm{ pp}}$ input signal range, and 80M $\Omega $ input impedance. The power consumption is $2.2\mu \text{W}$ at 0.8V analog and 0.6V digital supply voltages, and these correspond to a Schreier FoM of 165.2dB. Finally, the AFE properties are verified through several types of sensors.

This article presents a time-domain-controlled (TDC) single-inductor triple-output (SITO) step-up converter for portable devices with a bipolar power supply. A time-domain controller is utilized in the proposed converter to achieve a minimized delay time and thus ensure a high-conversion ratio (CR) with a switching frequency of 2 MHz. The proposed power converter employs a time-domain energy distribution (ED) balance scheme to ensure the bipolar outputs are symmetrically regulated. In addition, with the assistance of the output offset correction circuits, the load regulation of the TDC-SITO converter is greatly improved. By using an analog-to-digital converter (ADC)-assisted fast-settling loop, the converter achieves an excellent load transient response with low undershoot/overshoot voltages. Powered by a lithium-ion battery, the TDC-SITO converter can generate a bipolar power supply of $\pm$12 V and a standard 5 V output voltage, indicating a maximum CR of 8.8×. Implemented in a 180 nm bipolar-CMOS-DMOS (BCD) process, the converter achieves a peak conversion efficiency of 91.6% at an output power of 2.25 W. With a load current step of 100 mA between two output voltages of $\pm$10 V, the output voltages recover their normal values within 100 $\mu$s while the undershoot/overshoot voltages are below 160 mV. The maximum output power of the TDC-SITO converter is 9.6 W.