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Electroluminescence (EL) of MOS devices with rare-earth related oxide layer, which were fabricated with the mixtures of organic liquid sources of (Ce + Pr) and Gd spin-coated on the Si substrate and annealed, are reported. UV and visible white EL were observed. The spectral peaks of the EL correspond to radiative transitions of Pr3+, Ce3+, and Gd3+ ions. Effects of compounding ratios of (Ce + Pr) and Gd devices on EL characteristics are analyzed.

Temperature distributions and effects of metal wires on thermal properties in stacked 3-D ICs are analyzed with a test structure, which has a top tier chip attached on a bottom dummy chip with adhesive layer. The top tier chips were fabricated by a standard 0.18- $ {\mu }\text{m}$ CMOS process and their thickness ${t} _{{Si}}$ was thinned down to 20 $ {\mu }\text{m}$ . The test structure consists of 24 sensor blocks, each of which has sensor p–n diodes and an on-chip heater resistor, and selector switches. Various kinds of metal wire patterns on the sensor block surface have been examined their thermal effects. The temperature ${T}$ is proportional to the reciprocal of the distance ${L}$ for the single die (SD) device. For the thin ${t} _{ {Si}} {=} 20 {\mu }\text{m}$ stacked device, ${T}$ becomes a logarithmic function. Our thermal simulation results reveal that the heat flow in the thin ${t} _{ {Si}} {=} 20 {\mu }\text{m}$ device becomes 2-D in the chip, whereas the heat flow in the SD device is hemispherical. Although the metal wires decrease ${T}$ in the thinner device, the temperature reduction is relatively small even at the adjacent to the heater in the thin device. The simulation can produce temperature dependence similar to the measured results and consistent with the heat flow models. Metal wire patterns does not affect thermal transient phenomena, though the pulse heating response in the metal wire device without via and contact hole becomes lower due to the less heat transfer from metal wires to Si surface.

Temperature distribution in three tier stacked IC was analyzed with on chip measurement circuits, which were implemented in a specially designed LSI sandwiched between bottom and top dummy chips. Three kinds of LSI thickness , and 50\ μ m} were fabricated. The temperature distributions were analyzed with on-chip sensor arrays and heater resisters and compared with thermal simulation results. The thinner LSI with the stacked structure showed the higher LSI temperature, and the top dummy chip of the third tier reduced the temperature.

Electroluminescence (EL) of MOS devices with rare earth related oxide layer, which were fabricated with the mixtures of organic liquid sources of Tb and (Tb+Eu) spin-coated on the Si substrate and annealed, are reported. Visible green and red EL were observed. The spectral peaks of the EL correspond to radiative transitions of Tb3+ and Eu3+ ions. Effects of compounding ratios of (Tb+Eu) devices on EL characteristics are analyzed.

A test structure for analysis of temperature distribution in CMOS LSI is presented. Fundamental thermal properties of LSI chip have been measured and discussed with simulation results. The test structure consists of 24 sensor blocks, each of which has a resistor as an on-chip heater, a p-n diode or n-MOSFET array for temperature sensing and selector switches. Dependence of heating time and distance from the resistor are analyzed as well as transient phenomena. Temperature $T$ decreases with the distance $L$ , is proportional to the reciprocal of $L~(1/L)$ , and empirical equations have been proposed. The results of both p-n diode and n-MOSFET sensors are nearly the same. A thermal simulation gives an $L$ dependence of $T$ similar to the measured result. $T$ of 160 pin QFP becomes lower than that of 80 pin due to its larger outline, but $L$ dependence of $T$ is similar. The abrupt and gradual change of $T$ at the heater switching suggests both fast and slow processes in thermal conduction. The test structure can provide an effective methodology for analysis of fundamental thermal properties in LSIs packaged in various ways.

Glucose dehydrogenase from the thermoacidophilic archaeonThermoplasma volcanium(tvGlcDH) is highly active towards D-glucose and D-galactose, but does not utilize aldopentoses such as D-xylose as substrates. In the present study, the crystal structures of substrate/cofactor-free tvGlcDH and of a tvGlcDH T277F mutant in a binary complex with NADP and in a ternary complex with D-glucose and nicotinic acid adenine dinucleotide phosphate, an NADP analogue, were determined at resolutions of 2.6, 2.25 and 2.33 Å, respectively. The overall structure of each monomer showed notable similarity to that of the enzyme fromSulfolobus solfataricus(ssGlcDH-1), which accepts a broad range of C5 and C6 sugars as substrates. However, the amino-acid residues of tvGlcDH involved in substrate binding markedly differed from those of ssGlcDH-1. Structural comparison revealed that a decreased number of interactions between the C3-hydroxyl group of the sugar and the enzyme are likely to be responsible for the lack of reactivity of tvGlcDH towards D-xylose.

A test structure for analysis of temperature distributions and effects of metal wires on thermal properties in stacked IC is presented. The effects on the temperature distributions and transient phenomena in the single die and the stacked ICs were analyzed. The heat transfer in the metal wires affects the temperature distributions, which are consistent with the thermal simulation results. The test structure can provide an effective way for analysis of thermal properties in various LSIs.

Color tunable electroluminescence (EL) from metal–oxide–semiconductor devices with the rare-earth elements Tb and Eu is reported. Organic compound liquid sources of (Tb + Ba) and Eu with various Eu/Tb ratios from 0.001 to 0.4 were spin-coated on an n+-Si substrate and annealed to form an oxide insulator layer. The EL spectra had only peaks corresponding to the intrashell Tb3+/Eu3+ transitions in the spectral range from green to red, and the intensity ratio of the peaks was appropriately tuned using the appropriate Eu/Tb ratios in liquid sources. Consequently, the EL emission colors linearly changed from yellowish green to yellowish orange and eventually to reddish orange on the CIE chromaticity diagram. The gate current +I G current also affected the EL colors for the medium-Eu/Tb-ratio device. The structure of the surface insulator films analyzed by cross-sectional transmission electron microscopy (TEM), X-ray diffraction (XRD) analysis, and X-ray photoelectron spectroscopy (XPS) has four layers, namely, (Tb4O7 + Eu2O3), [Tb4O7 + Eu2O3 + (Tb/Eu/Ba)SiO x ], (Tb/Eu/Ba)SiO x , and SiO x -rich oxide. The EL mechanism proposed is that electrons injected from the Si substrate into the SiO x -rich oxide and Tb/Eu/Ba-silicate layers become hot electrons accelerated in a high electric field, and then these hot electrons excite Tb3+ and Eu3+ ions in the Tb4O7/Eu2O3 layers resulting in EL emission from Tb3+ and Eu3+ intrashell transitions.

We have investigated quantum electron transport in nanoscale double-gate MOSFETs using the multiband structure model for Si and the non-equilibrium Green function method. To obtain an accurate and realistic Si band structure, the empirical sp 3 s * tight-binding model including nearest and second-nearest neighbor coupling has been adopted. Especially, the dependence of the difference between the drain currents calculated from the present multiband and conventional effective mass models on the silicon layer thickness ( t Si ) has been examined. As t Si decreases below 3 nm, the current calculated from the multiband model becomes lower than that based on the effective mass model, and the difference between both currents increases. On the other hand, as t Si increases above 3 nm, the current from multiband structure calculations turns high compared to the current from effective mass calculations.

MOS capacitors with Si-implanted thermal oxide and CVD deposited oxide of 30nm thickness were fabricated for applications of non-volatile memory and electroluminescence devices. Current-voltage (I-V) and I-V hysteresis characteristics were measured, and the hysteresis window (HW) and the integrated charge of HW (ICHW) extracted from the hysteresis data were discussed. The HW characteristics of high Si dose samples showed the asymmetrical double-peaks curves with the hump in both tails. The ICHW almost converged after the 4th cycle and had the voltage sweep speed dependence. All +ICHW and -ICHW characteristics were closely related to the static (+I)-(+VG) and (-I)-(-VG) curves, respectively. For the high Si dose samples, the clear hump currents in the static I-VG characteristics contribute to lower the rising voltage and to steepen the ICHW increase, which correspond to the large stored charge in the oxide.

A test structure to analyze asymmetry and orientation dependence of MOSFETs is presented. n-MOSFETs with 8 different channel orientation and three kinds of process conditions were measured and symmetry characteristics of IDsat and IBmax with respect to the interchange of source and drain was examined. Although both IDsat and IBmax have similar channel orientation dependence, IBmax in interchanged S/D measurements shows asymmetrical characteristics, which can be applied to a sensitive method for device asymmetry detection.

The pH dependence of the reaction of various renins was investigated using sheep angiotensinogen as a substrate. Human renin showed two separate peaks, but rat and mouse Ren1 renins showed one peak with a shoulder. A comparison of the predicted subsite residues of human renin with those of rat and mouse Ren1 renins revealed that Arg82, Ser84, Thr85, Ala229, and Thr312 are unique in the human sequence. We examined the possible importance of these residues in the unique pH profile of the human renin reaction by replacing these residues with the corresponding residues of rat renin. The replacement of Ser84 of human renin with Gly changed the pH dependence of the reaction to one peak, similarly to rat and mouse Ren1 renins. Other mutant human renins kept two separate peaks, similarly to wild-type human renin. These results indicate that Ser84 of human renin contributes to the biphasic pH dependence of the renin-angiotensinogen reaction.

A computationally efficient and rigorous simulation method for treating dissipative electron transport in nanoscale, thin body, fully depleted SOI MOSFETs quantum-mechanically has been described. Within the non-equilibrium Green function (NEGF) formalism, scattering can be simply treated on the base of Buttiker probes. The probe strength is related to the low-field mobility, which depends on the electron subband and longitudinal position. Therefore, the low-field mobility for every subband at every position along the channel has been calculated using the eigenenergies and wave functions along the confinement direction and the Fermi level along the channel per self-consistent loop. As a result, the effect of scattering can be rigorously treated under the NEGF formalism. Our model has been applied to nanoscale n-channel double-gate MOSFETs and the results have been compared to those calculated with the conventional model. Moreover, the dependence of the output current on the silicon body thickness for the case with scattering has been investigated.

A test structure to separately analyze the location where the hot-carrier-induced CMOSFET reliability is determined around the center or the isolation-edge along the channel-width was proposed and fabricated. The test structure has four kinds of MOSFETs; [A] and [D] MOSFETs with a short and a long channel-length all over the channel width, respectively, [B] MOSFET with the short and the long channel-length around the center and the both isolation-edges, respectively, and [C] MOSFET with the channel-length regions vice versa to the [B] MOSFET. The time dependent changes of the threshold voltages V T , the saturation currents Is, the linear currents I L and the maximum transconductances β up to 50,000 s were measured. All data for the wide channel-width MOSFETs were almost categorized into three; [A], [B]/[C] and [D]. The [B]/[C] data were well estimated from simple theoretical discussions by the combination of [A] and [D] data, which mean that the reliabilities are nearly the same around the center or the isolation-edge for the CMOSFETs.

A test structure for reliability analysis of MOSFETs in CMOS inverters under DC and high frequency AC stress has been presented. It has an input pulse generation block with a ring oscillator, monitor inverter blocks and Kelvin connected selector switches. Detailed I – V characteristics of MOSFETs in the monitor inverters were measured and the degradation by HCI and BTI in nMOS and pMOS devices were analyzed. The dominant degradation origins in nMOS and pMOS devices can be attributed to HCI and NBTI, respectively.

A test structure to separately measure sheet resistances of highly-doped-drain (HDD) and lightly-doped-drain (LDD) in LDD-type CMOSFETs with various gate spaces S having sub-100 nm sidewalls was proposed. From the reciprocal of source/drain-resistance R -1 versus S characteristics, the sheet resistance ρ H of the high-conductive-region (HCR) corresponding to HDD and the approximate width W LC of the low-conductive-region (LCR) corresponding to LDD could be estimated. Both of ρ H and W LC for p- and n-MOS devices were scarcely dependent on the gate voltage. The sidewall-width difference of 40 nm could be sufficiently detected by using the test structure with the S pitch of about 60 nm. The R -1 versus S characteristics showed the unstable resistance variations in the narrow S region less than 0.3 μm, which corresponded to the minimum S for the process used for the test device fabrication and suggested that various micro-loading effects seriously affected on the characteristics.

A pure CMOS threshold-voltage reference (V TR ) circuit achieves temperature (T) coefficient of 5 μV/°C (T = -60 ∼ +100°C) and supply voltage (V DD ) sensitivity of 0.1 mV/V (V DD = 3 ∼ 5V). A combination of subthreshold current, linear current and saturation current in n-MOSFETs provides a small voltage and temperature dependence. Three different regions in I-V characteristics of MOSFETs generate a constant V TR based on threshold voltage at 0 K. A feedback scheme from the reference output to gates of n-MOSFETs extremely stabilizes the output. The circuit consists of only 17 MOSFETs and its simple scheme saves the die area, which is 0.18 mm 2 in the TEG (Test Element Group) chip fabricated by 1.2 μm n-well CMOS process.

A test structure and method for two-dimensional analysis of fabrication process variation of MOSFET using a photoemission microscope are presented. Arrays of 20×10 (=200) MOSFETs were successfully measured at a time and evaluated the fluctuation of their characteristics. The fluctuation of hot-carrier-induced photoemission intensity was larger as gate length becomes smaller. Although the intensity fluctuation of photoemission in the same MOSFET was within small range, the fluctuation all over the MOSFET array was relatively large and independent of the position in the array. An estimation method of the gate length.fluctuation has been demonstrated with the photoemission intensity distribution analysis.

Electroluminescence (EL) spectra under direct-current (dc) operation are reported for Au/SiO 2 /p-Si MOS capacitors with 50 nm Si-implanted SiO 2 . The transparent Au gate not only improves measurable wavelength range but also suppresses interference effects among MOS layers. The clear and smooth EL spectra have been measured and the EL spectrum was analyzed by fitting five Gaussian distribution functions. A model of EL emission mechanism is proposed for the Si-implanted MOS EL device. Furthermore, photomicrograph of blue EL emission is given, and a possibility of visible light emitting microdisplay device is demonstrated.

The gate direct tunneling current in sub-100-nm n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) in inversion regime has been calculated by solving the one-dimensional Schrodinger equations and two-dimensional (2D) Poisson equation self-consistently. This is the first 2D calculation of gate tunneling currents, although the model is not fully 2D. In the model, the wave-function penetration into the gate oxide and gate electrode is taken into account. The 2D effects of the gate tunneling current, in particular due to the edge direct tunneling (EDT) of electrons from the source and drain extensions, are investigated in detail. For lower gate voltages, the EDT current becomes a dominant component in the total gate current and exceeds the channel-to-gate current by three orders of magnitude at the maximum. Due to the EDT, the gate current is considerably dependent on the doping concentration and the gate overlapped length of the source and drain extensions.

This paper describes a new termination, feeder and aerial distribution cable for the feeder and distribution sections of access networks. These cables have great advantages in terms of cost and installation workability that will enable us to realize fiber-to-the-home (FTTH). First, we describe the cable requirements with regard to cost reduction and installation. Based on the requirements, we investigated and optimized the structural design of these cables. We manufactured these cables according to the results and confirmed that their transmission and mechanical characteristics are sufficiently stable for them to be used in access networks for FTTH.

The quantum-mechanical effects in counter doped n-channel metal–oxide–silicon field-effect transistors (MOSFETs) for metal gate complementary metal–oxide–silicon (CMOS) have been simulated using self-consistent calculations. The energy levels and fractional occupation of subbands, gate tunneling current and channel mobility in such metal gate MOSFETs have been investigated, comparing with those in n+-poly Si gate MOSFETs. The energy levels and fractional occupation for metal gate MOSFETs are fairly different from those for poly Si gate MOSFETs since the accumulation and inversion layers are formed on the respective surfaces by positive gate voltages. The tunneling current in metal gate MOSFETs is smaller than that in poly Si gate MOSFETs. In particular, at the gate voltages below 1 V, the current density is reduced by one order or above of magnitude. Moreover, the mobility in metal gate MOSFETs with lightly counter doped channel becomes much larger than that in poly Si gate MOSFETs because of the large suppression of ionized impurity scattering and surface roughness scattering.

The gate tunneling current in n+-polysilicon gate n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) in accumulation regime has been simulated quantum-mechanically. The two current components, due to hole tunneling from the accumulation layer on the p-silicon surface and due to electron tunneling from the accumulation layer on the n+-polysilicon gate, have been investigated for bulk and silicon-on-insulator (SOI) MOSFETs with various SOI layer thicknesses. For bulk MOSFETs, the electron current from the gate becomes much larger than the hole current from the silicon surface. On the other hand, as the SOI layer thickness (tSOI) decreases, the hole current increases, but the electron current decreases, and thus the hole current exceeds the electron current at a certain tSOI. The total gate current increases with decreasing tSOI (>2 nm). For extremely thin tSOI, the contribution of the electron current almost disappears. Moreover, the quantum-mechanical effects on the tunneling current in accumulated SOI MOSFETs have been discussed in detail.

The hole direct tunneling currents through ultrathin gate oxides have been calculated quantum-mechanically for not only bulk but also silicon-on-insulator (SOI) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with p+-polysilicon gates. In this work, the coupled Schrodinger and Poisson equations are solved self-consistently taking into account the wave-function penetration into the gate oxide and gate electrode completely. For bulk pMOSFETs, the experimental verification of the calculated hole tunneling current has been presented, and the effects of the wave-function penetration on quantization in the substrate have also been investigated. The hole tunneling currents in SOI pMOSFETs have been examined for various SOI layer thicknesses. Moreover, the quantum-mechanical effects on the tunneling current in ultrathin SOI pMOSFETs are discussed in detail.

As a component of the renin-angiotensin system, the (pro)renin receptor [(P)RR] activates prorenin along with intracellular signaling pathways. In this study, the glutathione S-transferase-fused extracellular domain of (P)RR expressed in mammalian cells was recovered in the detergent phase in detergent-based two-phase separation experiments, and intracellular localization was observed by immunocytochemistry, suggesting retention inside the cell through stable membrane association.

An 80-year-old man presenting with abdominal distension was admitted to our hospital. He was diagnosed with sigmoid cancer with multiple liver and lung metastases. We first performed a sigmoidectomy to avoid obstruction, and then initiated chemotherapy with S-1(120mg/day). The tumor showed a complete clinical response after 10 courses, but we had to change the regimen after 18 courses because of growth of the lung metastases. After 10 courses of capecitabine(4,200mg/ day)treatment, we again observed growth of the lung metastases; a new nodule, which was also considered to be a metastasis, appeared on the abdominal wall. We then decided to administer mFOLFOX6(5-fluorouracil+Leucovorin+oxaliplatin) after the patient had received oral anticancer drugs for 3 years 4 month. In conclusion, oral chemotherapy drugs may prevent tumor growth over a long period and improve quality of life(QOL)in elderly patients with Stage IV colon cancer.

We report a case of a patient with unresectable gastric cancer who showed complete response(CR)to S-1 and paclitaxel (PTX)combination therapy. The patient(a 67-year-old woman)was diagnosed with unresectable advanced gastric cancer with metastases in the Virchow's lymph nodes and para-aortic lymph nodes. Systemic chemotherapy with 70mg/m2 S-1 (days 1-14)and 70mg/m2 PTX(day 1)was administered every 3 weeks. At the end of 7 courses of chemotherapy, the primary lesion and swollen lymph nodes became markedly smaller. After 7 courses, an additional 39 courses were administered over 2.5 years. No notable adverse events were seen, and the patient's performance status(PS)was 0. CR was monitored by imaging studies. No cancer cells were detected on cytological examination of the primary lesion. Monotherapy with 70mg/m2 S-1(days 1-28, 2-week drug holiday)has been administered for the past 3 years. The patient is currently treated as an outpatient and maintains CR and a PS of 0.

Temperature distributions in three dimensional (3D) ICs were analyzed with a thermal simulation and compared with measured results of test 3D ICs, in which sensor p-n diode arrays and on chip heaters were embedded. The 3D IC consists of a top tier test chip and a 410 um thick bottom dummy chip. Both top tier chips and bottom dummy chips were fabricated by a standard 0.18 um CMOS process. The top tier chips had four kinds of the thickness of 50 through 410 um. The temperature distributions of the top tier test chip under the constant heater power were analyzed by both measurements and thermal simulations. The thinner top tier structures showed the higher temperature and affected the temperature distributions. Effect of various boundary conditions such as substrate size and peripheral bonding pads were examined with thermal simulation. The test structure and the simulation modeling can provide an effective way for analysis of thermal conduction in 3D ICs.

The inversion-layer mobility in future highly doped silicon-on-insulator (SOI) n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) has been examined for various SOI layer thicknesses (tSOI) using self-consistent calculation. Not only phonon scattering but also surface roughness scattering and ionized impurity scattering have been taken into account. It has been found for SOI MOSFETs with a highly doped channel that, whenever tSOI (≳2 nm) is reduced under the full-depletion condition, the inversion-layer mobility in SOI MOSFETs becomes higher than that in bulk MOSFETs. The increase in mobility with the reduction of tSOI to about 10 nm is mainly caused by the suppression of surface roughness scattering. Independent of acceptor concentration (NA), the mobility reaches its peak at tSOI of about 3 nm and then decreases drastically with decreasing tSOI. For SOI MOSFETs with NA higher than 5×1017 cm−3, the mobility increases monotonously to the peak with decreasing tSOI under the full-depletio...

An accurate and computationally efficient simulation method for quantum-mechanically treating dissipative electron transport in nanoscale double-gate metal–oxide–semiconductor field-effect transistors (DG MOSFETs) has been described. Within the nonequilibrium Green function formalism (NEGF), scattering can be simply treated on the base of Buttiker probes. The probe strength is related to the low-field mobility, which depends on the electron subband and longitudinal position. Therefore, the low-field mobility for every subband at every position along the channel has been calculated using the eigenenergies and wavefunctions along the confinement direction and the Fermi level along the channel per self-consistent loop. As a result, the effect of scattering can be rigorously treated under the NEGF formalism.

The temperature dependence of very-short-pulse-induced dynamic latchup in CMOS is studied over a temperature range of 77–400 K through two-dimensional device simulation with fulltemperature models. When the trigger-pulse duration decreases below 10 ns the temperature dependence of latchup immunity comes to disagree with the results of previous other studies, showing that latchup immunity increases with decreasing temperature. For very short pulses latchup immunity decreases monotonously or has its local maximum value at about 120 K and then decreases as the temperature decreases. Pulse-induced dynamic latchup sensitivity at 77 K exceeds that at 300 K when the pulse duration becomes shorter than a certain very small value. This temperature dependence mechanism of very-short-pulse-induced latchup is discussed in detail.

A test structure for analysis of temperature distribution in stacked IC, which has a top tier chip attached on a bottom dummy chip with adhesive layer, is presented. The devices with four kinds of thickness of 50–410 um were fabricated. Dependences of the temperature on distance from the heater resistor were analyzed with on-chip sensor arrays, as well as fast transient phenomena. The thinner top tier structures showed the higher temperature and affected the temperature distributions. The test structure can provide an effective way for analysis of thermal properties in various LSIs.

Blue/pink/purple electroluminescence (EL) from metal–oxide–semiconductor (MOS) devices with an indium tin oxide (ITO)/[Gd/(Ta + Gd/Pr)/(Pr + Ce)–Si–O] insulator layer/n+-Si substrate surface is reported. The insulator layers were fabricated from organic liquid sources of Gd or (Ta + Gd/Pr)/(Pr + Ce) mixtures, which were spin-coated on the n+-Si substrate and annealed at 950 °C for 30 min in air. The EL emission could be observed by the naked eye in the dark in the Fowler–Nordheim (FN) tunnel current regions. Peak wavelengths in the measured EL spectra were independent of the positive current. The EL intensity ratio of ultraviolet (UV) to the visible range varied with the composition ratio of the (Ta + Gd) liquids, and an optimum Ta to Gd ratio existed for the strongest blue emission, which could be attributed to the Ta-related oxide/silicate. The pink EL of the device fabricated with the ( ) mixture ratio can be explained by EL emission peaks related to the Pr3+ ions. The purple EL observed from the ( ) device corresponds to the strong and broad emission profile near the 357 nm peak, which cannot be assigned to Ce3+ ions. The results suggest that the EL can be attributed to the double-layer oxides with different compositions in the MOS devices. The upper layer consists of various Ta-, Gd-, Pr-, and Ce-related oxides and their silicates, while the lower SiO x -rich layer contributes to the FN current due to the high electric field, and thus the various EL colors.

The differences of electrical characteristics in trench-isolated n-well CMOSFET's with LDD- and EPS-regions fabricated by 7/spl deg/ and 0/spl deg/ tilt-angle phosphorous implantations are measured and qualitatively explained. The CMOSFET's have channel lengths ranging from 5 to 0.4 /spl mu/m and a channel width of 10 /spl mu/m. The differences in impurity profiles due to the channeling ions by 0/spl deg/-implantation cause the clear changes in the punchthrough-current characteristics and the substrate bias-voltage dependences of threshold voltages for both n- and p-MOSFET's. Meanwhile n- and p-MOSFET's fabricated by 7/spl deg/ and 0/spl deg/ implantations show nearly the same characteristics of threshold voltages and subthreshold swings which are almost determined by the impurity profiles in each channel region because the impurity profiles are scarcely affected by the channeling ions. >

A channel length engineering technique for optimization of primitive cells in standard cell libraries is effective for a leakage reduction method without significant increase of delay time, maintaining the same cell size. Reliability of NAND gates with series n-MOSFETs, which have modified channel length, have been analyzed under voltage stress condition with a test structure of ring oscillator implemented in standard 90 nm CMOS process. Stress time t strs dependence of degradation ratio of delay time t d and operation current I OP follow a power law of t strs . A channel length modification from 0.10 to 0.11 µm for the topmost n-MOSFET in series connected MOSFETs of NAND gates provides not only leakage current reduction but reliability improvement with less performance degradation under high voltage stress condition.

Two-dimensional (2-D) photon-energy distributions emitted from hot-carriers in LOCOS and trench-isolated CMOS devices with a narrow channel width of about 10 μm are measured. The 2-D photoemission images show different characteristics depending on the photon energy. Relatively large spatial fluctuations of normalized photoemission-intensity profiles for each photon energy are observed, while all the profiles show similar trapezoidal shapes along the channel width direction. Average electron temperatures are about 3700 and 3500 K for n- and p-MOSFETs, respectively, independently of the isolation technologies. Quite characteristic photoemission profiles and 2-D images are observed in trench-isolated n-MOSFETs after high bias-voltage stress.

Light emission-intensity profiles, images and nonuniform photon counts from reverse biased n/sup +/-diode fabricated by LOCOS and trench isolation are measured. Both spatial fluctuations of the emission profiles and nonuniform photon counts are relatively larger in trench-isolated diodes than those in LOCOS-isolated ones, and decrease as the reverse current increases. >

Subthreshold characteristics of CMOS devices become important for mixed signal SOCs (System On a Chip) [1]. Since matching of critical devices in important parameters such as I Dsat (saturation drain current), V T (threshold voltage), g m (transconductance) and S (subthreshold slope) are important in CMOS analog circuit design, channel orientation and current flow direction should be carefully arranged in LSI design. In this paper, orientation dependence and asymmetry of subthreshold characteristics in 0.18 μm p-MOSFET are analyzed using the test structure designed in our previous work [2].