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Implementations of artificial neural networks that borrow analogue techniques could potentially offer low-power alternatives to fully digital approaches

During last decade, various deep learning algorithms successfully broke the thick ice of AI winter so that they became an important part both in industries and daily lives [1]. They also invoked the development of AI accelerators (NPUs: neural processing units) that became a standard computing unit. This paper gives perspectives on various types of AI computing and device technology developments supporting them. An overview is given regarding how AI has widened its scope in material and semiconductor developments, and some important considerations are pointed out. Finally, the status of applying NISQ (noisy intermediate scale quantum) to material calculations is briefly discussed.

We present the world-first demonstration of 28-nm embedded MRAM (eMRAM) for frame buffer memory, highlighting the smallest macro size (0.08 mm2/Mb) reported to date. Compared to SRAM that is commonly used for frame buffer memory, eMRAM provides 47% area saving. For frame buffer applications, read disturbance and endurance are the most critical reliability considerations. With magnetic tunnel junction process improvements, we have verified sufficient read disturbance margins and met the endurance requirement (> 1E10 cycles) which corresponds to 10-year continuous usage. Compared to flash-type eMRAM, we have achieved 40% switching current reduction with < 50ns read/write speed.

In this paper we present a read circuitry that tackles all STT-MRAM read challenges. First, a negative temperature coefficient (NTC) reference based on an MTJ in series with an “NTC” resistor circuit emulator is described. Then, an offset cancelled voltage sense amplifier using low read current and reference averaging is discussed. Measurement results show a maximum of 2% reference impedance error (vs. ideal) and 1.7% read error rate degradation (vs. technology intrinsic defectivity rate). A 14.7Mb/mm2 memory density is also achieved, which is the best STT-MRAM published density for embedded applications.

High density 1Gb embedded STT-MRAM in 28nm FDSOI technology was successfully demonstrated. Based on the highly reliable and manufacturable eMRAM technology, high yield over 90% was achieved at the operating temperature from −40°c to 105°c with satisfying read, write function and 10 years retention at 105°c. These results are mainly attributed to the advanced process for better control of MTJ CD, highly manufacturable process window and robust circuit design for high density chip. MTJ properties can be systematically adjusted by tailoring the MTJ stack and MTJ module process. Improved endurance up to 1E10 cycles was achieved to broaden eMRAM applications to eDRAM replacement.

We successfully demonstrated the manufacturability of 8Mb STT-MRAM embedded in 28nm FDSOI logic platform by achieving stable functionality and robust package level reliability. Read margin were greatly improved by increasing TMR value and also reducing distribution of cell resistance using advanced MTJ stack and patterning technology. Write margin was also increased by improving the efficiency using novel integration process. Its product reliability was confirmed in package level with passing HTOL 1000 hours tests, 106 endurance test, and retention test. For a wider application, we also demonstrated the feasibility of high density 128Mb STT-MRAM. Based on these results, we clearly verified the product manufacturability of embedded STT-MRAM.

RESET distribution of phase-change random access memory (PRAM) is highly related to heat fluctuations during RESET write (RESET W ). In this work we investigate the effect of load resistance (R L ) with constant voltage write method and propose new RESET W method with an optimal R L selection equation with considering Joule heating and thermoelectric effects. Since the optimal R L compensates for intrinsic dynamic resistance variation in PRAM, the heat fluctuation is reduced and the RESET distribution is improved. With fabricated PRAM TEG, we verify that optimal RL exists and achieve more improved RESET distribution with the optimized R L by 41% than with R L not optimized.

In this paper, we present a designed single Magnetic Tunnel Junction (MTJ) cell and a single switching transistor (1T-1MTJ) bitcell based 8Mb 64 I/O Spin-Transfer-Torque Magnetic RAM (STT-MRAM). Novel 3-Section Symmetric Reference Structure and high-gain Single-stage cross-coupled Sense Amplifier (SA) are implemented. The developed chip has about 40% decreased area and power consumption when compared to the same process 2T-2MTJ STT-MRAM or SRAM chips with equal memory bit size. The achieved read time is lesser than 10ns at worst MTJ and Process-Voltage-Temperature corner. Failed bit counts are fewer by 1.7% for MTJ's Tunnel Magneto-Resistance (TMR) higher 150%. This chip has demonstrated complete SRAM compatibility by passing all the tests in the display TCON (Time Controller).

We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion beam etching (IBE) process was optimized with power, angle, and pressure to reduce a short fail below 1 ppm. Through these novel technologies, we demonstrated highly functional and reliable 8Mb eMRAM macro having a wide sensing margin and strong retention property of 85 0C and 10yrs.

We evaluated the limit of scaling bottom electrode contact (BEC) heater size and high resistivity heater to reduce writing current. It was found that the resistivity of heater should be increased for reducing writing current below the heater size of about 50 nm without any undesirable increase of resistance of the crystalline state (SET state, Rset). It was shown in the numerical simulations that the dissipated heat loss through BEC during melting GST was decreased in the increase of resistivity of heater. In addition, we analyzed the resistance components contributing to the total set resistance. It was observed that the undesired sharp increase of Rset as the BEC size decreases below 50 nm was attributed to the resistance component of GST–BEC interface. In the case of high resistivity heater, the contributions of both incomplete crystallization and heater itself were enhanced.

We successfully developed 256Mb Phase Change Random Access Memory (PRAM) based on 0.10μ m-CMOS technologies using ring type contact. The writing current with uniform CD process variation of Bottom Electrode Contact (BEC) was achieved by improving CMP process and developing core dielectric material. Also, the ring type contact scheme provided strong reliability such as the cycling endurance and data retention time for 256 Mb high density PRAM.

An advanced bottom electrode contact (BEC) was successfully developed for reliable high-density 256 Mb phase-change random access memory (PRAM) using a ring-type contact scheme. This advanced ring-type BEC was prepared by depositing very thin TiN films inside a contact hole, after which core dielectrics were uniformly filled into the TiN-deposited contact hole. Using this novel contact scheme, it was possible to reduce reset current while maintaining a low set resistance and a uniform cell distribution. Thus, it has been clearly demonstrated that the use of the ring-type contact technology is very feasible for high-density PRAM beyond 256 Mb.

A nonvolatile 16-kb one-transistor one-magnetic-tunnel-junction (1T1MTJ) magnetoresistance random access memory with 0.24-/spl mu/m design rules was developed by using a self-reference sensing scheme for reliable sensing margin. This self-reference sensing scheme was achieved by first storing a voltage of the magnetic tunnel junction (MTJ), and then after a time interval storing a reference voltage of the same MTJ (self-reference). The effects of variation in tunneling oxide thickness can be eliminated by this self-reference sensing scheme. As a result, reliable sensing of MRAM devices with MTJ resistance of 2.5-11 k/spl Omega/ was achieved.

In this paper, a 0.15 /spl mu/m embedded DRAM technology is described which provides a cost-effective means of delivering high bandwidth, low power consumption, noise immunity, and a small foot print chip. The key technologies for high performance transistors are dual thickness gate oxide, dual work-function gate with Si/sub 3/N/sub 4/ capped Ti polycide, and selective Co silicidation of source/drain diffusion by Si/sub 3/N/sub 4/ liner. In order to increase the memory cell efficiency, all memory cell contacts in DRAM arrays are formed by self-aligned contact (SAC) etching. Low temperature Al/sub 2/O/sub 3/ stacked cell capacitor with hemispherical grain (HSG) makes it possible to realize the sufficient storage capacitance in DRAM arrays and the high performance transistor. The CMP planarization of interlayer dielectric enlarges the depth of focus for lithography and enables the multilevel metallization. These integration technologies can be fairly extendible to the future embedded DRAM in 0.13 /spl mu/m technology node and beyond.

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction.

This paper presents, for the first time, the Active Width Modulation (AWM) technology which compensates a string resistance with the active widths of local Y selectors for the purpose of increasing the number of cells-per-string (CPS). The AWM is demonstrated using 58 nm 512 Mb PRAM with 32 CPS instead of 8 CPS [1], which can reduce the chip size by 4.3%. Also, the systematic variability of a program current, ΔI PGM , is reduced from 17.8% to 0.82%, and that of a write energy, ΔE PGM , from 47.9% to 2.0%. Both write endurance and disturbance of >1M cycles are achieved for 512 Mb PRAM. The AWM can be further applied to increase CPS to 64 or 128, together with the reduction of a reset current, I RESET , for sub-40 nm PRAM technology and so on.

We investigate the key factors for scalable high density MRAM. Specifically we examine problems such as large switching field, small sensing margin and writing disturbance following a decrease in size. We demonstrate these problems and suggest several solutions for realizing high density MRAM.

For the prospects on future semiconductor memory, the key technical limits of future technology scaling in conventional memories and the directions to overcome the problems are reviewed. In addition, we reviewed the technical challenges and opportunities of emerging new memories such as FRAM (ferroelectric RAM), MRAM (magnetic RAM) and PRAM (phase-change RAM) which has been recently focused as candidates for idea memory which can solve the problems of conventional memories.

Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6 mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR flash memory compatible interfaces. Therefore, the fabricated chip was tested under the mobile application platform and its functionality and reliability has been evaluated by operation temperature dependency, disturbance, endurance, and retention. Finally, it was clearly demonstrated that high density PRAM can be fabricated in the product level with strong reliability to produce new nonvolatile memory markets.

Phase change RAM (PRAM) is a promising memory that can solve the problems of conventional memory - scalability, write/read speed and reliability. The process technologies for the integration of high density PRAM are reviewed. The most important challenge of PRAM is the reduction of writing current. Various approaches to reduce the writing current are reviewed and other key factors for the high density PRAM are discussed.

A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18-/spl mu/m CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30/spl deg/ C.

There have been concerns about how far we can extend the so far so successful conventional semiconductor memories Such as DRAM, SRAM and Flash memory and what will be the future directions of memory development. In this article, we will review the key technical limits of conventional memory scaling and the directions to overcome the problem. In addition, we will review the technical challenges and opportunities of emerging. new memories such as ferroelectric RAM (FRAM), magnetic RAM (MRAM) and phase change RAM (PRAM) which has been recently focused as candidates for ideal memory which can solve the problems of conventional memories.

PRAM is a promising memory that can solve the problems of conventional memory. Writing current reduction is the most important technical challenges in order to maximize the advantage of PRAM in scaling. We will present the high density 64Mb PRAM based on 0.18 /spl mu/m CMOS technologies. And Various approaches to reduce the writing Current will be reviewed.

PRAM(Phase-Change RAM) is a promising memory that can solve the problems of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. We presented process factors which affect the writing current and the result of improvement. Finally we demonstrated results of 64Mb PRAM integration based on 0.18/spl mu/m CMOS technology.

We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 /spl mu/m-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge/sub 2/Sb/sub 2/Te/sub 5/, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for RESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.

By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.

The technological challenges associated with STTM (scalable two transistor memory) cells were reviewed. First of all, the basic operating principles of the memory cell are discussed. This is followed by the introduction of the memory array formation and co-process of the I/O transistor, applying a 0.24 /spl mu/m design rule test vehicle. A new cell structure of a surrounded gate STTM structure is introduced. In addition, the process technology and the performance of the memory cell are presented.

We have fully integrated a nonvolatile random access memory by successfully incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. As well as basic characteristics of the memory operation, we have also observed reliable performances of the device on hot temperature operation, endurance against repetitive phase transition, writing imprint, reading disturbance and data retention.

We have integrated a 64Mb nonvolatile random access memory using phase transition phenomena. Based on 0.18/spl mu/m-CMOS technologies, the vertical contact typed memory cell is fabricated. The device density can be sharply increased with decreasing the writing current and the GST size. But for reduction of writing current, issues including set and interface resistances should be stabilized. Additionally, our results also show the feasibility of 256Mb nonvolatile PRAM with writing time below 100ns.

Data retention time has been investigated for mass-produced 512 Mb DRAMs with 0.12 /spl mu/m design rules. Cell junction leakage components were analyzed for the first time using a test structure. It was found that process-induced trap density and electric field at the storage node (SN) junction should be reduced to control leakage current and thus data retention time. Moreover, we propose a novel cell transistor using localized channel and field implantation (LOCFI) which greatly suppresses the ion implantation damage and reduces the electric field at the same time. Finally, data retention time has been improved by 3/spl sim/4 times due to the LOCFI cell transistor with optimized process conditions.

In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.

The preferred oriented texture Ge2Sb2Te5 (GST) thin film was prepared on SiO2∕Si(001) and TiN(60nm)∕Si(001) substrates. With the modulated layers of each constituent materials, the stoichiometry of thin film was controlled. Through cross section transmission electron microscope analysis and the x-ray diffraction (XRD) measurement at different temperatures, the evolutions of as-grown multilayer from amorphous to textured crystalline state were studied. Highly preferred orientation to ⟨00l⟩ direction of GST film was verified by XRD pole figure measurements to deduce the orientation distribution function. From these results, the authors could suggest the effective synthetic method to make the texture GST film with high crystalline quality.

A switching method called by field assisted spin switching has been investigated. A field assisted spin switching consists of a metal line induced magnetic field and a spin switching through a magnetic tunnel junction. It is a variation of a current induced switching and assisted by the magnetic field induced by the current-carrying metal line. Various current paths have been tested to investigate how and how much the spin switching contributes to the overall switching and the results will be explained. A computer simulation has been complemented to measure the degree of the thermal effect in the switching.

By replacing the traditional single magnetic free layer in magnetic random access memory (MRAM) with a synthetic antiferromagnetic (SAF) layer composed of two antiferromagnetically coupled layers, the possibility of the kink generation has been suppressed to a minimum level and the normalized free-layer shift has been reduced from 15% to less than 5%. These phenomena are thought to be from the reduction of the effective thickness and magnetic moment by introducing a SAF free layer. Since the SAF free layer decreases the magnetostatic interaction with the pinned layer, free-layer shift is also decreased. A SAF free layer forms a closed magnetic loop between two antiferromagnetically coupled layers. Therefore, it increases a tendency to become a single domain and its switching field distribution is enhanced. With the optimized SAF free layer, array quality factor [AQF, σ(Hc)∕Hc] is increased to more than 10 and switching window could be obtained which is the area to be selectively switched in the memory cel...

We present a new simulation methodology for analyzing programming characteristics of a chalcogenide based phase-change device, phase change random access memory (PRAM), which is a next-generation non-volatile memory. Using the new simulation methodology, we analyze the initialization of chalcogenide material (ICM) of the mechanism and propose the next generation PRAM scheme. From the results of the phase change simulation, the process conditions for ICM for stable operation are presented. Also, the self-heating confined structure to overcome the inherent limitation of high operation power is proposed that resolves the operating power limitation associated with PRAM development.

Phase-change random access memory is considered a potential challenger for conventional memories, such as dynamic random access memory and flash memory due to its numerous advantages. Nevertheless, high reset current is the ultimate problem in developing high-density phase-change random access memory (PRAM). We focus on the adoption of Ge2Sb2Te5 confined structures to achieve lower reset currents. By changing from a normal to a GST confined structure, the reset current drops to as low as 0.8 mA. Eventually, our integrated 64 Mb PRAM based on 0.18 µm CMOS technology offers a large sensing margin: R reset ∼200 kΩ and R set ∼2 kΩ, as well as reasonable reliability: an endurance of 1.0×109 cycles and a retention time of 2 years at 85°C.