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Copyright of Micronanoelectronic Technology is the property of Micronanoelectronic Technology Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

To realize the automated welding of mounted chips and solve the problems of low efficiency and poor yield rate of manual welding, the detection and localization algorithm of mounted chips and solder joints based on machine vision is proposed. Firstly, to improve the efficiency of the algorithm, we propose a region filtering algorithm with minimized interference to extract image regions of interest (ROI). Secondly, the region-connected domain method is proposed to obtain the set of weld ball centers of gravity and then calculate the radius of the welding ball and the number of empty points. After that, an improved linear fitting method is utilized to calculate the chip body size, average pitch of solder balls, and rotation angle information. Finally, the method proposed in this paper is validated by performing experimental tests on 12 different mounted chips. The experimental results show that the detection accuracy of this method can reach 5 µm for the offset amount and 20 µrad for the angle deviation amount, and the detection time of the unit welding ball is kept within 1.03 ms. Compared with the traditional algorithm, the detection speed is improved while guaranteeing detection accuracy. [ABSTRACT FROM AUTHOR]

Defect inspection of IC devices is getting more challenging with the increase of package density. Scanning acoustic microscopy (SAM) is widely used in electronic industry. The detection resolution is, however, limited by the penetration depth of ultrasound. It is necessary to find a way to improve the resolution and accuracy. A new strategy of multi-scale decomposition and fusion based on the wavelet transform was proposed to enhance the image resolution in SAM detection. The original SAM image was subjected to wavelet decomposition at different scales. Two recombined images A and B were decomposed into low frequency band (cAd1 and cAd2) and high frequency bands (cHd1, cVd1, cDd1, and cHd2, cVd2, cDd2), which were then merged respectively based on the local area energy. A high resolution SAM image was reconstructed by using the new coefficients. Back propagation network modified with genetic algorithm (GA-BP) was utilized to classify the solder joints. The proposed scheme achieved highest recognition accuracy (97.16%) compared with other methods. The new strategy provides an effective way to enhance the image quality and recognition accuracy in SAM detection of micro defect. [ABSTRACT FROM AUTHOR]

The nano-silver-coated tin (Sn@Ag) paste was modeled using the method of the Anand unified viscoplastic constitutive model and elastic model. After thermal cyclic loading, the plastic strain of the solder joints increased cumulatively, while the maximum equivalent stress remained basically stable. The simulation results show that the maximum displacement occurs at the solder joint at the farthest end from the center of the chip, which is a dangerous solder joint. Using the finite element method and EPRI (the American Electric Power Research Institute) estimation method, the fatigue life of the nano-silver-coated tin solder joint is predicted to be 616 weeks, which is significantly higher than that of the nano-silver solder joint. It is indicated that adding a certain amount of nano-tin to the nano-silver paste to form a core–shell structure can improve the shear strength of the solder joint and reduce the plastic strain, thereby significantly improving the reliability of the solder joint. It is proved by experiments that the nano-silver paste is feasible for flip–chip interconnection. The research on this topic provides experimental reference and theoretical basis for the application of a new generation of interconnection materials in power devices and promotes the development and application of microelectronic packaging technology.

In this paper, the reliability of copper pillar micro-bump under random vibration is investigated. Three kinds of copper pillar solder joints with different morphologies were obtained by changing the hot press bonding process, and the random vibration fatigue simulation of flip-flop interconnect solder joints was carried out by using Ansys to obtain the stress–strain distribution law of the solder joints and predict the vibration fatigue life of the solder joints. It is found that the outermost solder joints of flip-flop bonding are most likely to fail; the fatigue life of copper pillar solder joints is predicted based on the three interval method, the Miner linear cumulative damage criterion and the high cycle fatigue formula; reliability experiments are conducted, and it is found that the drum solder joints are most prone to cracking, followed by hourglass and columnar shapes and that all cracks are caused by the substrate side of copper pillar. Cracks are sprouted from the contact surface between the copper pillar and solder on the substrate side and expand internally in the intermetallic compound (IMC) layer, while the presence of voids aggravates the generation of cracks. [ABSTRACT FROM AUTHOR]

Flip chip bonding technology on gold–tin (Au-Sn) microbumps for MEMS (Micro Electro Mechanical Systems) and 3D packaging is becoming increasingly important in the electronics industry. The main advantages of Au-Sn microbumps are a low electrical resistance, high electrical reliability, and fine pitch. However, the bonding temperature is relatively high, and the forming mechanism of an intermetallic compound (IMC) is complicated. In this study, Au-Sn solid-state diffusion (SSD) bonding is performed using the thermal gradient bonding (TGB) method, which lowers bonding temperature and gains high bonding strength in a short time. Firstly, Au-Sn microbumps with a low roughness are prepared by using an optimized process. Then, Au-Sn bonding parameters including bonding temperature, bonding time, and bonding pressure are optimized to obtain a higher bonding quality. The shear strength of 23.898 MPa is obtained when bonding in the HCOOH environment for 10 min at the gradient temperature of 150 °C/250 °C with a bonding pressure of more than 10 MPa. The IMC of Au-Sn is found to be Au-Sn and Au5Sn. The effect of annealing time on the IMC is also investigated. More and more Au5Sn is generated with an increase in annealing time, and Au5Sn is formed after Sn is depleted. Finally, the effect of annealing time on the IMC is verified by using finite element simulation, and the bonding strength of IMC was found to be higher when the bonding temperature is 150 °C at the cold side and 250 °C at the hot side. The temperature in the bonding area can reach 200 °C, which proves that the Au-Sn bonding process is solid-state diffusion because the temperature gradient reaches 2500 °C/cm. [ABSTRACT FROM AUTHOR]

Scanning acoustic microscopy (SAM) technique has been applied to defect inspection in electronic devices. With the increase of packaging density, detection of the micro-defects in high density devices becomes more and more challenging. The SAM test is suffering from sacrificing the spatial resolution to reach a certain penetration depth of the ultrasonic waves. So it is necessary to enhance the resolution level of the SAM image. In this paper, a wavelet based resolution enhancement technique was investigated to reconstruct a high quality image for SAM test of the flip chip packages. The stationary wavelet transform was adopted to decompose the captured SAM image into four frequency subbands, and the high frequency subbands were enhanced by adding the difference matrix in the intermediate stage, and a super resolution SAM image was derived from combining all the subbands by using the Inverse Discrete Wavelet Transform. Then the solder joints segmented from the SR-SAM image were classified by using the SVM algorithm. The results validated that the proposed technique is effective to improve the detection accuracy of SAM test. • An intelligent system is developed to inspect the solder joints of flip chip. • The SAM image is decomposed into four different frequency components. • High resolution SAM image is reconstructed with the wavelet-based method. • The solder joints are segmented from the SR-SAM image. • The SR-SAM image has high accuracy for defect recognition. [ABSTRACT FROM AUTHOR]

In superconducting quantum processors, the predictability of device parameters is of increasing importance as many laboratories scale up their systems to larger sizes in a 3-D-integrated architecture. In particular, the properties of superconducting resonators must be controlled well to ensure high-fidelity multiplexed readout of qubits. Here, we present a method, based on conformal mapping techniques, to predict a resonator's parameters directly from its 2-D cross-section, without computationally heavy and time-consuming 3-D simulation. We demonstrate the method's validity by comparing the calculated resonator frequency and coupling quality factor with those obtained through 3-D finite-element-method simulation and by measurement of 15 resonators in a flip-chip-integrated architecture. We achieve a discrepancy of less than 2% between designed and measured frequencies for 6-GHz resonators. We also propose a design method that reduces the sensitivity of the resonant frequency to variations in the interchip spacing.

Flip chip bonding technology on gold–tin (Au-Sn) microbumps for MEMS (Micro Electro Mechanical Systems) and 3D packaging is becoming increasingly important in the electronics industry. The main advantages of Au-Sn microbumps are a low electrical resistance, high electrical reliability, and fine pitch. However, the bonding temperature is relatively high, and the forming mechanism of an intermetallic compound (IMC) is complicated. In this study, Au-Sn solid-state diffusion (SSD) bonding is performed using the thermal gradient bonding (TGB) method, which lowers bonding temperature and gains high bonding strength in a short time. Firstly, Au-Sn microbumps with a low roughness are prepared by using an optimized process. Then, Au-Sn bonding parameters including bonding temperature, bonding time, and bonding pressure are optimized to obtain a higher bonding quality. The shear strength of 23.898 MPa is obtained when bonding in the HCOOH environment for 10 min at the gradient temperature of 150 °C/250 °C with a bonding pressure of more than 10 MPa. The IMC of Au-Sn is found to be Au-Sn and Au5Sn. The effect of annealing time on the IMC is also investigated. More and more Au5Sn is generated with an increase in annealing time, and Au5Sn is formed after Sn is depleted. Finally, the effect of annealing time on the IMC is verified by using finite element simulation, and the bonding strength of IMC was found to be higher when the bonding temperature is 150 °C at the cold side and 250 °C at the hot side. The temperature in the bonding area can reach 200 °C, which proves that the Au-Sn bonding process is solid-state diffusion because the temperature gradient reaches 2500 °C/cm.

Solder fatigue failure is one of the primary wear-out failure mechanisms limiting reliability in microelectronics flip chip packaging. Solder fatigue failure occurs when a crack initiates and subsequently propagates through the entirety of the solder joint causing an electrical open. Crack initiation and propagation within a solder joint is caused by a cyclic application of stress, typically induced by exposure to temperature cycle excursions. Understanding the relationship between thermal cycling during product use and the accelerated thermal cycles used for testing is critical for predicting device reliability. MIL-PRF-38535 is the guiding aerospace and high-reliability General Specification for Integrated Circuits (Microcircuits) Manufacturing that defines manufacturing, qualification, and certification requirements for products to be listed on the Defense Logistic Agency’s (DLA) Qualified Manufacturer Listing (QML). Revision M of this standard, released in November 2022, for the first time includes the use of lead-free solder alloys and organic substrates in the manufacturing of QML flip chip products. Hence, there is a strong need to understand the physics-of-failure (PoF) concerning solder fatigue of lead-free flip chip assemblies. This article demonstrates how finite element modeling can be used to predict solder fatigue for flip chip package assemblies. The authors have leveraged fatigue lives measured for different flip chip daisy chain package configurations, as well as fatigue lives defined and available in published papers. The authors then use the resulting leadfree solder fatigue model to perform parametric studies looking at the impact of different die sizes, underfill material properties, and package substrate materials. Comparisons are also made between eutectic Sn/Pb and lead-free fatigue life predictions. In addition, the authors demonstrate how solder fatigue predictions can be de-rated to use conditions in order to make reliability assessments for flip chip package assemblies. This ultimately leads to a better understanding of the impact of solder alloy and material selection on the mission life of aerospace and high reliability products that fall under the changes introduced in MIL-PRF-38535 Revision M. [ABSTRACT FROM AUTHOR]

Plasma treatment changes the surface morphology and transforms the surface energy. Therefore, it was applied before the underfill (UF) process of the flip chip to improve the wettability and adhesion of the UF and to prevent delamination or voids. This study focuses on the plasma effects of the regions beneath the flip chip, which comprise the widely used plasma gases, i.e., Ar, N2, and O2. The effects of the plasma treatments are analyzed using atomic force microscopy, X-ray photoelectron spectroscopy, and Dyne ink tests. The surface roughness of the substrate (SBT) center regions is increased from 183.9 nm (bare SBT) to 232.8 nm after the O2 plasma treatment, and the surface roughness of the die center regions is increased from 14.5 to 17.2 nm. The surface-area difference percentage also increases from 47.4% to 61.7% for the SBT center region and from 24.0% to 34.0% for the die center region. The resultant surface energy also increases from 60 to 84 mN/m for the SBT center region and from 66 to 84 mN/m for the die center region. Based on these results, it can be stated that O2 plasma is more effective than other gas plasmas for surface activation, especially beneath the die region. [ABSTRACT FROM AUTHOR]

Flexible electronics such as mechanically compliant displays, sensors and solar cells, have important applications in the fields of energy, national defence and biomedicine, etc. Various types of flexible electronics have been proposed or developed by the improvements in structural designs, material properties and device integrations. However, the manufacturing of flexible electronics receives little attention, which limits its mass production and industrialization. The increasing demands on the size, functionality, resolution ratio and reliability of flexible electronics bring several significant challenges in their manufacturing processes. This work aims to report the state-of-art technologies and applications of flexible electronics manufacturing. Three key technologies including electrohydrodynamic direct-writing, flip chip and automatic optical inspection are highlighted. The mechanism and developments of these technologies are discussed in detail. Based on these technologies, the present work develops three kinds of manufacturing equipment, i.e., inkjet printing manufacturing equipment, robotized additive manufacturing equipment, and roll-to-roll manufacturing equipment. The advanced manufacturing processes, equipment and systems for flexible electronics pave the way for applications of new displays, smart sensing skins and epidermal electronics, etc. By reviewing the developments of flexible electronics manufacturing technology and equipment, it can be found that the existing advances greatly promote the applications and commercialization of flexible electronics. Since flexible electronics manufacturing contains many multi-disciplinary problems, the current investigations are confronted with great challenges. Therefore, further developments of the reviewed manufacturing technology and equipment are necessary to break the current limitations of manufacturing resolution, efficiency and reliability. [ABSTRACT FROM AUTHOR]

With the development of electronic products toward high density and high reliability, the size of interconnect solder joints and interconnect pitch continues to decrease. Under normal service conditions, solder joints are subjected to thermal–electric–mechanical loads simultaneously, resulting in reliability problems for many package structures. This article investigated the effects of interconnect shape and thermal-electro-migration on solder creep of copper-pillar flip chip joints and analyzed the corresponding failure modes and mechanisms. In this article, solder joints with different shapes were obtained by adjusting the thermal compression bonding process parameters, and creep experiments were performed on the solder joints under different temperature and stress conditions. In addition, we have performed thermoelectric coupling experiments and finite element simulations for different shapes of solder joints. Moreover, creep experiments were conducted on three types of solder joints after 10 and 40 h of thermoelectric coupling pretreatment. The results show that the three solder joints exhibit typical creep characteristics under different experimental conditions and the creep strain rate increases with the increase of shear stress and temperature. Under the same conditions, the creep strain rate of the hourglass-shaped solder joint is always higher than that of the other two solder joints. The electromigration reliability of the hourglass-shaped solder joint is the worst, and the electromigration reliability of the cylinder-shaped solder joint is the best. With the increase of thermoelectric coupling pretreatment time, the creep strain rate of solder joints increased significantly, and the fracture mode of solder joints gradually changed from ductile fracture to brittle fracture. Among the three types of solder joints, the creep resistance of the hourglass-shaped solder joints is greatly affected by the thermoelectric coupling pretreatment. [ABSTRACT FROM AUTHOR]

Flip chip (FC) light emitting diodes (LEDs) are considered to be more promising in solid state lighting as compared to wire bonded LEDs. For solid-state lighting, thermal management is a very critical factor to enhance the device's performance. In the Flip Chip Light Emitting Diode (LED), the active region is the main source of heat generation. This heat is to be conducted through different layers to the heat sink. The adhesive layer and bump assembly cause heat dissipation because of their low conductivity values and poor transparency and hence cause degradation in performance of FC-LEDs. In this paper, thermal analysis of flip chip LED is done to find out how material, size of die and bumps affect the thermal performance of FC-LED. A flip chip LED structure is modeled on a GaN substrate. Different material properties of silicon, gold, and aluminum have been studied to perform the thermal analysis and to see the effects of different die sizes, bump sizes, and adhesive materials. Thermal analysis of the high-power FC LED by using the Finite Element Method is done on Ansys Software. The FC structure and its meshing design are presented.Temperature variation with different sizes of bump, chip-die and different adhesives (silver filled epoxy, Au-Sn, Pb-Sn) on flip chip LED is discussed. The result shows that thermal heat is directly proportional to the size of the bump and the type of adhesive material selected also affects the performance of FC-LEDto some extent. [ABSTRACT FROM AUTHOR]

This paper proposes a novel nondestructive diagnostic method for flip chips based on an improved semi-supervised deep extreme learning machine (ISDELM) and vibration signals. First, an ultrasonic transducer is used to generate and focus ultrasounds on the surface of the flip chip to excite it, and a laser scanning vibrometer is applied to acquire the chip'on signals. Then, an extreme learning machine-autoencoder (ELM-AE) structure is adopted to extract features from the original vibration signals layer by layer. Finally, the study proposes integrating the ELM with sparsity neighboring reconstruction to diagnose defects based on unlabeled and labeled data. The ISDELM algorithm is applied to experimental vibration data of flip chips and compared with several other algorithms, such as semi-supervised ELM (SS-ELM), deep ELM, stacked autoencoder, convolutional neural network, and ordinary SDELM. The results show that the proposed method is superior to the several currently available algorithms in terms of accuracy and stability. [ABSTRACT FROM AUTHOR]

Printing technology and mounting technology enable the novel field of hybrid printed electronics. To establish a hybrid printed system, one challenge is that the applied mounting process meets the requirements of functional inks and substrates. One of the most common requirements is low process temperature. Many functional inks and substrates cannot withstand the high temperatures required by traditional mounting processes. In this work, a standardized interconnection and an automated bump-less flip-chip mounting process using a room temperature curing conductive adhesive are realised. With the proposed process, the conductive adhesive selected for the standardized interconnection can be dispensed uniformly, despite its increase of viscosity already during pot time. Electrical and mechanical performance of the interconnection are characterized by four terminal resistance measurement and shear test. The herein proposed automated process allows for fabrication of hybrid printed devices in larger batch sizes than manual assembly processes used beforehand and thus, more comprehensive evaluation of device parameters. This is successfully demonstrated in a first application, a novel hybrid printed security device. The room temperature mounting process eliminates any potentially damaging thermal influence on the performance of the printed circuits that might result from other assembly techniques like soldering. [ABSTRACT FROM AUTHOR]

Sensors are the key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently, the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow the reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project "eHarsh" to overcome this hurdle. In the course of the project, an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor frontend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high-temperature 0.35-micron SOI-CMOS technology focusing operating temperatures up to 300°C. The chipset is assembled on a multilayer ceramic low-temperature cofired ceramics (LTCC) board using flip chip technology. The ceramic board consists of four layers with a total thickness of approximately 0.9 mm. The internal wiring is based on silver paste while the external contacts were alternatively manufactured in silver (sintering/soldering) or in gold alloys (wire bonding). As an interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high-quality flip chip interconnects can be generated. [ABSTRACT FROM AUTHOR]

A simple method for the prediction of the heavy ion-induced single event effect cross-section based on proton experimental data has been proposed, which is convenient for flip chips. The method relies on the effective LET spectrum of protons in the sensitive layer of microelectronic devices. Two chips using different packaging technologies are selected to verify this method, and the results obtained by our method are consistent with the heavy ion experimental data. The principle of this method has been analyzed in depth, and the limitations are also given. [ABSTRACT FROM AUTHOR]

The present paper studied rapid preparation of uniform BAG solder balls for aviation microcircuit maintenance by utilizing uniform droplet ejection technology. The effects of the nozzle diameter, the driving signal pulse width and amplitude, and the ejection temperature on the solder ball size were studied respectively. The uniformity, sphericity, and internal quality of the prepared solder balls were also analyzed. The results illustrate that the pulse width and spray temperature are no significant influence parameters; The nozzle diameter is a strong correlation parameter of the ball size; The driving signal amplitude is also a significant influence parameter. The particle size can be adjusted according to the nozzle diameter and the driving signal amplitude. The uniformity of solder balls generated from different nozzle sizes is less than 5% of their average diameter, indicating a high spherical degree of the solder balls. Finally, metallographic photos of the solder balls reveal uniform and dense internal structures. This paper provides a novel method for rapid preparing uniform solder balls of flip chips in aviation equipment maintenance. [ABSTRACT FROM AUTHOR]

Ultraviolet detectors are widely used in space exploration, military affairs, and disinfection. To further improve the responsivity and response time, we propose and demonstrate AlN three-dimensional metal-semiconductor-metal (3D-MSM) and flip chip 3D-MSM (FC-3DMSM) ultraviolet detector here. The performance of devices with different etching depth and electrode spacing has been investigated using APSYS simulation. According to the simulation results, we fabricated 0.5 μm-etched 3D-MSM (3D-MSM-0.5 &#956m) and 1.3 μm-etched FC-3DMSM (FC-3DMSM-1.3 μm) devices. Response time is decreased by 29.3% and 13.8% for 3D-MSM-0.5 μm and FC-3DMSM-1.3 μm devices, and responsiveness exhibits a 20.5% and 46.6% improvement at 200nm, compared with traditional MSM device. This is due to varied internal electric field distribution of 3D-MSM and FC -3DMSM device configuration, which accelerates the collection of photo-generated carriers and improves the carrier collection efficiency. Our work should advance the development of nitrides ultraviolet detectors. [ABSTRACT FROM AUTHOR]

Abstract This paper proposes a new encapsulation structure for aluminum nitride-based deep UV light-emitting diodes (DUV-LEDs) and eutectic flip chips containing polydimethylsiloxane (PDMS) fluid doped with SiO2 nanoparticles (NPs) with a UV-transparent quartz hemispherical glass cover. Experimental results reveal that the proposed encapsulation structure has considerably higher light output power than the traditional one. The light extraction efficiency was increased by 66.49% when the forward current of the DUV-LED was 200 mA. Doping the PDMS fluid with SiO2 NPs resulted in higher light output power than that of undoped fluid. The maximum efficiency was achieved at a doping concentration of 0.2 wt%. The optical output power at 200 mA forward current of the encapsulation structure with NP doping of the fluid was 15% higher than that without NP doping. The optical output power of the proposed encapsulation structure was 81.49% higher than that of the traditional encapsulation structure. The enhanced light output power was due to light scattering caused by the SiO2 NPs and the increased average refractive index. The encapsulation temperature can be reduced by 4 °C at a driving current of 200 mA by using the proposed encapsulation structure.

Interfacial residual stress resulting from coefficient of thermal expansion mismatch between different layers of the flip-chip joint is induced during the bonding process. The flip-chip joints suffer residual stresses that may cause cracking or delamination, which is one of the major reliability issues in electronic packaging. This paper theoretically analyzes the interfacial residual stress of the flip-chip joint based on anisotropic conductive adhesive (ACA). The residual stress model is established based on refined zigzag theory (RZT). Results show that the theoretical model and the simulation analysis are consistent. It is found that the interfacial thermal residual stress in the ACA layer is uneven and reaches its peak at the end of the bump. The RZT model is validated by experiments, and the model prediction agrees well with the test results.

Copyright of Chinese Journal of Liquid Crystal & Displays is the property of Chinese Journal of Liquid Crystal & Displays and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Printing technology and mounting technology enable the novel field of hybrid printed electronics. To establish a hybrid printed system, one challenge is that the applied mounting process meets the requirements of functional inks and substrates. One of the most common requirements is low process temperature. Many functional inks and substrates cannot withstand the high temperatures required by traditional mounting processes. In this work, a standardized interconnection and an automated bump-less flip-chip mounting process using a room temperature curing conductive adhesive are realised. With the proposed process, the conductive adhesive selected for the standardized interconnection can be dispensed uniformly, despite its increase of viscosity already during pot time. Electrical and mechanical performance of the interconnection are characterized by four terminal resistance measurement and shear test. The herein proposed automated process allows for fabrication of hybrid printed devices in larger batch sizes than manual assembly processes used beforehand and thus, more comprehensive evaluation of device parameters. This is successfully demonstrated in a first application, a novel hybrid printed security device. The room temperature mounting process eliminates any potentially damaging thermal influence on the performance of the printed circuits that might result from other assembly techniques like soldering.

Copyright of Chinese Journal of Liquid Crystal & Displays is the property of Chinese Journal of Liquid Crystal & Displays and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Smaller, lighter, faster, cheaper are today demands; new technologies stack and interconnect materials and components are utilised to achieve high density, small size, low weight, reduced power, and very low cost. Particularly important in this context is the implementation of higher densities, reduced volume hand in hand with improved reliability. A good price-performance ratio is key. [ABSTRACT FROM AUTHOR]

In this paper, a novel technique is proposed to provide a 3D piezoresistive MEMS stress sensor with a real-time self-monitoring of its bonding status. Perceiving the degradation of this interlayer due to different environmental parameters is crucial for reliable electronics and sensors assembly. The utilized sensor is featuring strain technology to fully extract the six stress components. Whenever a multilayer assembly, such as a sensor on a structure, is subjected to thermal or mechanical load, out-of-plane shear stress will accumulate at its edge as a reaction for peeling. As any degradation in the adhesion layer causes a significant reduction for out-of-plane shear stress, the capability of the 3D chip to measure this stress is employed to detect the degradation of the adhesive layer. To verify the capability of the current concept to experimentally quantify this loss, thermal energy is exploited for softening the bonding film. Losses up to 28 % for the out-of-plane shear stress are detected at a temperature equal to 80°c, which causes 71.9 percent decrease in the modulus of elasticity of the utilized adhesive. This significant correlation, between the out-of-plane shear stress loss and the bonding layer stiffness, is used to obtain a full picture of the adhesive deterioration in an early phase. The same technique can be utilized as a low profile detector for the debonding in multilayer electronics. [ABSTRACT FROM AUTHOR]

Residual deformation evaluation of underfill (UF) materials in flip chips is crucial to improve the reliability of electronic packages. In this study, we propose to evaluate the residual thermal strain distributions using an inverse method based on the sampling moiré technique. Even if a grid pattern is fabricated on the specimen at room temperature, the residual strain distributions at an arbitrary temperature relative to the specimen formation temperature can be successfully calculated. The residual strain distributions relative to the free contraction state at an arbitrary temperature can also be measured when the coefficient of thermal expansion is available. A thermal chamber for flip chips was designed under a laser scanning microscope. Using the proposed method, the normal, shear and principal internal strain distributions and deformation characteristics of two kinds of UFs in flip chips were investigated relative to 150 °C. The strains of the UF with low glass transition temperature (UF-A) concentrate near the die material, especially at the die corner, while the strain concentration of the underfill with high glass transition temperature (UF-B) mainly occurs at the die corner and the buffer layer. The maximum principal strain of UF-A is greater than that of UF-B around the die corner. The residual maximum principal strain distributions relative to the free contraction state at 25 °C were compared with the simulation results by the finite element method. The residual strain distribution trends from experiments are consistent with those from simulations. [ABSTRACT FROM AUTHOR]

This article investigates how floor plan layout of a printed circuit board (PCB) influences the reliability of the component’s solder joint connections when operated in a vibrating environment. A random vibration profile as seen in an automotive environment was used in full lifetime tests. An industry-standard FR4 PCB with electroless nickel immersion gold (ENIG) surface finish was manufactured with double-sided component placement including 14 flip chips, eight on the top side and six on the bottom side. Ultrasound scans were used as a nondestructive test to assess the integrity of solder joints from manufacture to failure. This enabled monitoring of the important interface between solder joints and flip chip where failure mostly occurs. The initial failure pattern was found by experiment where 86 cycles of random vibration caused all flip chips to mechanically fail. Failure followed a Weibull probability with a value of $\beta = 1.297$ , indicating that failure rates increase with time. The results show that the reliability of a flip chip varies with its position on a PCB with some marked differences to component lifetimes. The results also show that for two-sided flip-chip placements on a PCB, back-to-back, overlapped, and single-sided orientations have subtle effects on flip-chip lifetimes. Similarly, reliability varied with solder joint positions since joints on the sides of a flip chip nearest the PCB edges were less reliable than those on sides on a flip chip furthest away. Finally, design guidelines are offered to effect the most reliable flip-chip placement on a two-sided PCB when operated in a vibrating environment. [ABSTRACT FROM AUTHOR]

In this article, flip chip assembly using nonconductive films (NCFs) was evaluated for chip-on-board (COB) packages using Cu/Sn–Ag hybrid bumps. In general, significant thermomechanical stress can be induced at the Cu-pillar/Sn–Ag solder joint because of a large coefficient of thermal expansion (CTE) mismatch between the Si chip and printed circuit board (PCB). If a concave-shaped solder joint morphology is generated at the solder joint, thermomechanical stress could be concentrated at the solder joint, resulting in an early failure of T/C reliability. To obtain the solder joint morphology without a concave-shaped solder joint, NCFs’ curing properties and viscosity should be controlled. In particular, the NCFs’ viscosity at the solder melting temperature, at which metallurgical bonding between molten solder and Cu pads occurs, will significantly affect the solder joint morphology. For this reason, solder joint formation was investigated at each viscosity of NCFs and bonding temperature during the thermo compression (TC) flip chip bonding process. In addition, specific viscosities at certain bonding temperatures during the flip chip bonding process were obtained from measured degrees of cure and viscosity approximation. Finally, the material properties of NCFs were optimized without NCF traps at the solder joint and concave-shaped solder joint, and T/C reliability was evaluated for each silica powder content. As a result, it was confirmed that the COB packages using Cu/Sn–Ag hybrid bumps and optimized NCFs show stable resistance changes within 10% of the initial resistance after the T/C reliability test. [ABSTRACT FROM AUTHOR]

Due to the recent rapid industrialization and urbanization across the world, chemicals are released into the environment at an unprecedented rate. Gas sensors, in particular, interferometric based devices represent an important toolkit for air quality monitoring. Amongst different interferometers, linear variable filter (LVF) holds the promise of a fixed optical component that can be operated under various conditions. In this work, oxide pillars were deposited on a [Si-SiO2] mirror coated wafers. Thick oxide deposition was performed using a low temperature high density chemical vapor process with photoresist as mask to form pillars. By sandwiching two such substrates together, a milli-degree taper angle was formed by a difference in pillar height. The mated normal incidence LVF was demonstrated with an operating range of $0.7~\mu \text{m}$ , full width half maximum of 230 nm at 3,500 nm and was tested for the presence of acetone vapor. The relationship between transmission intensity and acetone concentration was plotted with a correlation R2 of 0.972. [ABSTRACT FROM AUTHOR]

Flip chip technology has been widely used in various fields. As the density of the solder balls in flip chip technology is increasing, the pitch among solder balls is narrowing, and the size effect is more significant. Therefore, the micro defects of the solder balls are more difficult to detect. In order to ensure the reliability of the flip chip, it is very important to detect and evaluate the micro defects of solder balls. High-frequency ultrasonic testing technology is an effective micro-defect detection method. In this paper, the interaction mechanism between high-frequency ultrasonic pulse and micro defects is analyzed by finite element simulation. A transient simulation model for the whole process of ultrasonic scanning of micro defects is established to simulate scanning in acoustic microscopy imaging. The acoustic propagation path map is obtained for analyzing acoustic energy transmission during detection, and the edge blurring effect in micro-defect imaging detection is clarified. The processing method of the time-domain signal and cross-section image signal of micro defects based on sparse reconstruction is studied, which can effectively improve the accuracy of detection and the signal-to-noise ratio. [ABSTRACT FROM AUTHOR]