394 results on '"Cheng-Kok Koh"'
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2. A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems.
3. Clustering of flip-flops for useful-skew clock tree synthesis.
4. Scalable Construction of Clock Trees With Useful Skew and High Timing Quality.
5. Saath: Speeding up CoFlows by Exploiting the Spatial Dimension.
6. Clock Tree Construction based on Arrival Time Constraints.
7. Saath: Speeding up CoFlows by Exploiting the Spatial Dimension.
8. Delay-driven layer assignment for advanced technology nodes.
9. Construction of Latency-Bounded Clock Trees.
10. MCMM clock tree optimization based on slack redistribution using a reduced slack graph.
11. Fast clock scheduling and an application to clock tree synthesis.
12. A Useful Skew Tree Framework for Inserting Large Safety Margins.
13. Human-pose estimation with neural-network realization.
14. Rubik: Unlocking the Power of Locality and End-point Flexibility in Cloud Scale Load Balancing.
15. Fast clock skew scheduling based on sparse-graph algorithms.
16. Construction of reconfigurable clock trees for MCMM designs.
17. Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression.
18. An Automatic Design of Factors in a Human-Pose Estimation System Using Neural Networks.
19. MIP-based detailed placer for mixed-size circuits.
20. A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness.
21. A study on the use of parallel wiring techniques for sub-20nm designs.
22. Analytical placement of mixed-size circuits for better detailed-routability.
23. Selecting best viewpoint for human-pose estimation.
24. Cost-Effective Robustness in Clock Networks Using Near-Tree Structures.
25. Local merges for effective redundancy in clock networks.
26. Case study for placement solutions in ispd11 and dac12 routability-driven placement contests.
27. Collaborative object tracking with motion similarity measure.
28. Using action classification for human-pose estimation.
29. A 3D-point-cloud feature for human-pose estimation.
30. Optimization of placement solutions for routability.
31. A size scaling approach for mixed-size placement.
32. Mixed integer programming models for detailed placement.
33. A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing.
34. Cross link insertion for improving tolerance to variations in clock network synthesis.
35. Synthesis of low power clock trees for handling power-supply variations.
36. Processor caches with multi-level spin-transfer torque ram cells.
37. Simultaneous redundant via insertion and line end extension for yield optimization.
38. How to Improve Your Google Ranking: Myths and Reality.
39. PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation.
40. A study of routability estimation and clustering in placement.
41. The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.
42. A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction.
43. How to Improve Your Search Engine Ranking: Myths and Reality.
44. A 3-D-Point-Cloud System for Human-Pose Estimation.
45. Optimal post-routing redundant via insertion.
46. Guiding global placement with wire density.
47. A fast band matching technique for impedance extraction.
48. Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.
49. A frequency-domain technique for statistical timing analysis of clock meshes.
50. A fast band-matching technique for interconnect inductance modeling.
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