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Your search keyword '"2.5D stacking"' showing total 4 results
Start Over Descriptor "2.5D stacking" Publication Year Range Last 50 years
4 results on '"2.5D stacking"'

1. Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip.

Author

Dadashi, Sajed, Reza, Akram, Reshadi, Midia, and Khademzadeh, Ahmad

Subjects
*ROUTING algorithms, *SILICON, *TOPOLOGY
Abstract

Stacking technology is an approach to improve scalability of 2D network-on-chip systems. 3D stacking technology places multiple chips vertically, while silicon chips are stacked side-by-side on a silicon interposer layer in the 2.5D stacking technology. 2.5D stacking can solve many of the 3D stacking difficulties such as thermal problem. The cores in the processing element (PE) layer must have the ability to connect together. Moreover, the connection between the processing cores and the other chips is a critical issue that should be concerned. The memory chip is one of the most important chips, integrated with the many-core chip. The network-on-chip can be extended to the interposer layer to increase the usability of the interposer layer. It is essential to have an efficient topology and deadlock-free routing algorithm to handle operations effectively and decrease delay and power consumption. In this paper, a new topology called "Balanced Mesh" and a deadlock-free routing algorithm is recommended that balances fairly the connection between different Mesh-based segments of a network. Many of interposer network topologies such as ButterDonut increase the degree of intermediate routers in the interposer layer or nodes related to other chips. Many of them cannot be easily used in the PE layer to have a uniform system. The proposed topology can be simply applied to both of many-core layer and the interposer layer to decrease delay and power consumption without any change in the degree of nodes and has lesser number of links. Our proposed topology is compared with some other topologies such as concentrated Mesh(CMesh) and ButterDount. Simulation results show that our proposed topology can improve the system efficiency with lesser number of links. Using our proposed topology in both layers achieves 13% improvement in network latency compared with using Mesh in the PE layer and ButterDonut in the interposer layer. Also, it achieves 12% improvement in power consumption. [ABSTRACT FROM AUTHOR]

Published
2019
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2. 400 Gbps 2-Dimensional optical receiver assembled on wet etched silicon interposer

Author

Ripalta Stabile, Finn Kraemer, Chenhui Li, Oded Raz, Teng Li, Electro-Optical Communication, Eindhoven Hendrik Casimir institute, Low Latency Interconnect Networks, and Semiconductor Nanophotonics

Subjects
Fabrication, Optical fiber, Materials science, Silicon, business.industry, Optical interconnects, chemistry.chemical_element, 2.5D stacking, 02 engineering and technology, Pseudorandom binary sequence, law.invention, Silicon ineterposer, 020210 optoelectronics & photonics, CMOS, chemistry, law, 0202 electrical engineering, electronic engineering, information engineering, Optoelectronics, Fiber, Transceiver, business, Electrical impedance, 2-dimensional optical transceiver
Abstract

In this paper, based on a wet etched silicon interposer, we propose a 2.5D assembly of two dimensional optical transceivers for 400 Gbps parallel optical interconnections. In this opto-electronic packaging, two dimensional optical matrix is formed as 250 μm in both the x -and y-directions by exploiting commercial opto-electronic arrays, and a compact optical interface is used to couple the light channels with fiber ribbons. Each quadrant of the optical matrix is connected with its CMOS IC part via impedance matched co-planner wave guides. The shortest traces between optics and CMOS ICs can be 300 μm, benefiting from flip-chip technology. The process flow of silicon interposer fabrication is illustrated. With flip-chip bonding, 25 Gbps 2D 16-channel receiver is assembled on the silicon interposer, and the sub-module, including the optical interface, is scaled down to 4 mm by 6 mm. In addition, the performance of this assembled module is fully characterized. Uniform and clear eye patterns are captured for all of the channels. Receiver sensitivities are also tested for all channels at 25.78 Gbps, 2 31-1 PRBS, with the variation less than 1.5 dB at error free operation.

Published
2018

3. 400 Gbps 2-Dimensional optical receiver assembled on wet etched silicon interposer

Author

Li, Chenhui, Stabile, Ripalta, Kraemer, Finn, Li, Teng, Raz, Oded, Li, Chenhui, Stabile, Ripalta, Kraemer, Finn, Li, Teng, and Raz, Oded

Abstract

In this paper, based on a wet etched silicon interposer, we propose a 2.5D assembly of two dimensional optical transceivers for 400 Gbps parallel optical interconnections. In this opto-electronic packaging, two dimensional optical matrix is formed as 250 μm in both the x -and y-directions by exploiting commercial opto-electronic arrays, and a compact optical interface is used to couple the light channels with fiber ribbons. Each quadrant of the optical matrix is connected with its CMOS IC part via impedance matched co-planner wave guides. The shortest traces between optics and CMOS ICs can be 300 μm, benefiting from flip-chip technology. The process flow of silicon interposer fabrication is illustrated. With flip-chip bonding, 25 Gbps 2D 16-channel receiver is assembled on the silicon interposer, and the sub-module, including the optical interface, is scaled down to 4 mm by 6 mm. In addition, the performance of this assembled module is fully characterized. Uniform and clear eye patterns are captured for all of the channels. Receiver sensitivities are also tested for all channels at 25.78 Gbps, 2 31-1 PRBS, with the variation less than 1.5 dB at error free operation.

Published
2018

4. Wet etched silicon interposer for the 2.5D stacking of CMOS and optoelectronic dies

Author

Oded Raz, Barry Smalbrugge, Tjibbe de Vries, Ripalta Stabile, Chenhui Li, Electro-Optical Communication, NanoLab@TU/e, Low Latency Interconnect Networks, and Semiconductor Nanophotonics

Subjects
Materials science, Through-silicon via, Silicon, business.industry, Hybrid silicon laser, Optical interconnects, chemistry.chemical_element, 2.5D stacking, 02 engineering and technology, Electrical connection, 020210 optoelectronics & photonics, chemistry, 0202 electrical engineering, electronic engineering, information engineering, Interposer, Optoelectronics, Wafer, Photonics, 3D stacking, business, Lithography
Abstract

In this paper, we demonstrate a way of packaging CMOS ICs and optoelectronics, which has been achieved by using a deeply wet etched silicon interposer. The silicon interposer concept is used for the assembly of electronics (drivers, TIAs), photonics (VCSELs, PDs) and mechanical optical interface (MOI) and can be fabricated on full wafers. Only four steps of lithography are needed to fabricate the silicon interposer and both sides of this interposer are utilized for electrical and optical connections. The impedance matched metal traces and gold bumps for electrical connection are lithographically transferred and electro-plated. The optical vias are also opened by wet etching. The process is performed on a diced 1 inch silicon wafer, 4 interposers are made with one process flow. The obtained silicon interposers are used for 12 × 10G transmitter and 4 × 25G transceiver. The process challenges for the 3D patterning of the silicon interposer and for the metal traces definition are discussed. Data integrity experiments are performed.

Published
2016

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