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An 8.8-mW, low-noise, 40.5-GHz frequency synthesizer is proposed. The synthesizer system consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a 900-MHz high-frequency-reference (HFR) PLL, and a novel subsampling lock detector (SSLD). The SSLD keeps monitoring the locking status of the SSPLL by sampling the SSPLL output with the HFR 900-MHz reference and automatically controls the SSPLL for frequency acquisition if it loses lock or locks to a wrong 100-MHz harmonic. This is done without using a power-consuming divider-based frequency-locked loop in conventional SSPLL. Due to the relatively low-frequency operation and moderate noise requirement of HFR, as well as the low-power SSLD, the proposed system achieves low power consumption and jitter simultaneously. The measured results show 8.8-mW power consumption and 228-fs rms jitter with in-band and out-band phase noises of −96.6 dBc/Hz at a 1-MHz offset and −106.9 dBc/Hz at a 10-MHz offset, respectively. [ABSTRACT FROM AUTHOR]

In this article, we present a 438–479-GHz fully integrated 25-element radiator array source based on a scalable structure of coupled standing wave oscillator cells without extra loss and parasitics from coupling networks. The bandwidth is extended using a varactor-less frequency tuning method, and EIRP is improved by increasing the size of the array using the proposed scalable coupling method and maximizing the radiation directivity using a silicon lens in an optimized radiation setup. An analysis of the radiation directivity of a chip-lens setup is presented as well as the employed approach for enhancing EIRP by maximizing the directivity. The circuit is implemented in a 65-nm CMOS process and is measured to have 40.7 GHz/8.9% frequency tuning range. The chip consumes 0.38–2.34-W power (1.18 W at 459-GHz center frequency) from a 1.2-V supply voltage. The circuit provides a maximum of −1.8-dBm radiated power and 19.3-dBm EIRP at 448 GHz using a 12.5-mm radius silicon lens. The minimum measured phase noise at 10-MHz offset is −100.6 dBc/Hz. To the best of our knowledge, this article has the largest EIRP, radiated power, and bandwidth among fully integrated silicon-based coherent sources above 350 GHz. [ABSTRACT FROM AUTHOR]

This article presents a 230-GHz wideband harmonic voltage-controlled oscillator (VCO) with large output power based on a compact and low-loss structure of coupled standing wave oscillators. In order to boost the output power, oscillators are coupled together without adding extra passive loss to the circuit. Transistors with inductive drain impedances provide the necessary negative resistance to the oscillators while simultaneously acting as active variable capacitors for frequency tuning and generate the desired second-harmonic power through their nonlinearities. Transmission lines at the drains are responsible for creating the inductive impedance as well as coupling adjacent oscillators and routing and combining the output power. Therefore, the circuit has a compact structure that minimizes passive losses. A varactor-less frequency tuning scheme is used and allows for wideband operation without sacrificing the output power. In addition to oscillator coupling and minimizing the losses, the output power has been boosted by engineering the harmonic impedance that is seen by the transistors in the circuit. The prototype chip was implemented in a 65-nm CMOS process. The output power of the VCO covers 219–238 GHz frequency band (8.35% tuning range) and delivers 3.4-dBm maximum output power. The minimum measured phase noise is −105.8 dBc/Hz (at 10-MHz offset) while consuming 195 mW from a 1.5-V supply. [ABSTRACT FROM AUTHOR]

In this paper, a 0.34-THz $2\times 2$ phased array integrated circuit is presented, which demonstrates a new approach for implementing phased arrays in the millimeter-wave (mm-wave)/terahertz (THz) spectrum. The circuit structure consists of four unit standing wave oscillators. In each cell, fundamental frequency ($f_{0}$) and odd harmonics are systematically cancelled, while the desired fourth harmonics ($4f_{0}$) are combined and radiated by on-chip patch antennas. A phase-shifter-less mechanism is employed based on combining standing and traveling waves to create the required phase shift between the sources for beam steering. The transistors provide negative resistance to the circuit and generate the desired fourth harmonics through nonlinearity. Simultaneously, transistors are employed as active variable capacitors for varactor-less frequency tuning. The implemented phased array is capable of independent wideband frequency tuning and 2-D wide-angle beam steering. The circuit is fabricated in a 0.13- $\mu \text {m}$ SiGe BiCMOS process and is measured to have 52-GHz/15.1% frequency tuning range from 318 to 370 GHz and 128°/53° 2-D beam-steering angle. The chip consumes 310–640 mW power from a 1.5-V supply with −6.8-dBm maximum radiated power and minimum −93.1-dBc/Hz phase noise at 10-MHz offset. To the best of our knowledge, this paper has the largest bandwidth among fully integrated THz radiator/phased arrays as well as the widest angle beam steering among fully integrated THz phased arrays. [ABSTRACT FROM AUTHOR]

Based on piecewise linear modeling of field-effect transistors, harmonic translations are deployed to analyze the fundamental limits for a maximum second-harmonic power generation for any given field-effect transistor. Optimum waveforms at the gate–source and drain–source terminals, which yield high second-harmonic power generation by the given transistor, are derived. Two oscillators are implemented in a TSMC 65-nm CMOS process. Transistors in these oscillators have optimum voltage waveforms at their terminals. Thus, they deliver a state-of-the-art second-harmonic output power while operating at relatively higher frequencies than related arts. One of the proposed oscillators has the maximum output power of 4.9 dBm and a peak dc-to-RF efficiency of 3% at 300 GHz. Each of the implemented oscillators occupies 0.16 mm2 of the chip area. [ABSTRACT FROM AUTHOR]

In this paper, we present a new architecture for implementation of millimeter-wave (mm-wave) and terahertz (THz) radiator arrays based on standing-wave properties. This structure is a continuous distributed coherent array that avoids lossy and parasitic coupling networks. Moreover, it can be scaled simply by extending the size of the structure and replicating the unit cell. The absence of coupling parasitics in addition to the unique characteristics of standing waves allows us to extend the tuning range without using varactors. The 0.34-THz four-element radiator array is designed and fabricated in a 130-nm SiGe BiCMOS process using microstrip transmission lines as the standing-wave mediums and on-chip patch antennas to radiate the desired fourth harmonic of the oscillation. The circuit was measured with no post processing or silicon lens and has 5.9% frequency tuning range (332.5–352.8 GHz) with less than 6-dB output power variation across the band. It consumes 425-mW power from 1.8-V supply and the radiated power is −10.5 dBm at center frequency with −98.2 dBc/Hz phase noise at 10-MHz offset frequency. [ABSTRACT FROM PUBLISHER]

Based on time-variant behavior of metal-oxide–semiconductor field-effect transistors in large-signal operations, harmonic translations and their mutual effects are analyzed. Large amplitudes at terminal voltages of these transistors push them into different regions of operation. In this paper, harmonic translations are derived as a result of such changes in operation region of transistors. Operation in triode region for a portion of oscillation cycle results in iterative harmonic translations between fundamental frequency and second harmonic. They boost each other constructively for significantly stronger oscillation, more second harmonic output power, and enhanced dc-to-RF efficiency. Based on this analysis, a 215-GHz signal source, implemented in a TSMC 65-nm CMOS LP is presented. The proposed oscillator achieves a maximum output power of 5.6 dBm and a dc-to-RF efficiency of 4.6%. The measured phase noise is −94.6 dBc/Hz at 1-MHz offset. The proposed oscillator occupies only 0.08 mm2 of chip area. [ABSTRACT FROM PUBLISHER]

A 300 GHz frequency synthesizer incorporating a triple-push VCO with Colpitts-based active varactor (CAV) and a divider with three-phase injection is introduced. The CAV provides frequency tunability, enhances harmonic power, and buffers/injects the VCO fundamental signal from/to the divider. The locking range of the divider is vastly improved due to the fact that the three-phase injection introduces larger allowable phase change and injection power into the divider loop. Implemented in 90 nm SiGe BiCMOS, the synthesizer achieves a phase-noise of –77.8 dBc/Hz (–82.5 dBc/Hz) at 100 kHz (1 MHz) offset with a crystal reference, and an overall locking range of 280.32–303.36 GHz (7.9%). [ABSTRACT FROM AUTHOR]

We introduce a novel frequency tuning method for high-power terahertz sources in CMOS. In this technique, multiple core oscillators are coupled to generate, combine, and deliver their harmonic power to the output node without using varactors. By exploiting the theory of nonlinear dynamics, we control the coupling between the cores to set their phase shift and frequency. Using this method, two high-power terahertz VCOs are fabricated in a 65 nm LP bulk CMOS process. The first one has a measured output power of 0.76 mW at 290 GHz with 4.5% tuning range and the output power of the second VCO is 0.46 mW at 320 GHz with 2.6% tuning range. The output power of these signal sources is 4 orders of magnitude higher than previous CMOS VCOs and is even higher than VCOs implemented in compound semiconductors with much higher cut-off frequencies. [ABSTRACT FROM AUTHOR]

In this paper, we study an electrical nonlinear medium consisting of voltage-dependent capacitors and inductors to generate sharp pulses from a lower frequency sinusoid. First, we analyze the optimum conditions for maximum harmonic generation in a uniform nonlinear line. Next, we extend the nonlinear line to a two-dimensional nonlinear lattice that is compatible with CMOS technology. Compared with the nonlinear line, the lattice relies on spatial power combining, higher cut-off frequency, and nonlinear wave interaction to enhance the pulse amplitude and sharpness. To show the feasibility of this method, we implement the first CMOS nonlinear lattice in a 0.13-\mum CMOS process, and successfully demonstrate 2.7-Vpp, 6.3-ps pulses from a 22-GHz input signal. [ABSTRACT FROM AUTHOR]

A wideband frequency multiplier that effectively generates and combines the even harmonics from multiple transistors is proposed. It takes advantage of standing-wave formation and loss cancellation in a distributed structure to generate high amplitude signals resulting in high harmonic power. Wide bandwidth operation and odd harmonic cancellation around the center frequency are the inherent properties of this frequency multiplier. Using this methodology, we implemented a frequency doubler that operates from 220 GHz to 275 GHz in a standard 65 nm CMOS process. Output power of -6.6 dBm (0.22 mW) and conversion loss of 11.4 dB are measured at 244 GHz. [ABSTRACT FROM AUTHOR]