Search

We have developed neuromorphic computing based on Analog ReRAM, Resistive Analog Neuromorphic Device (RAND), as low power solution for edge application. We have proposed perceptron circuit which has resistive elements to store weights as analog resistance and binarizes output from each layer in order to realize large scale integration and keep high accuracy. We have fabricated 180nm test chip by using mass production process and we have demonstrated MNIST recognition and sensor application in flexible network architecture in which several neural networks can be configured at the same time. We present potential of low power solution by scaling down to 40nm node under development and reliability issues to be considered in neural network processors based on analog nonvolatile memories.

We present reliability issues to be considered in neural network (NN) processors based on analog nonvolatile memories. We developed a reliability model of resistive random access memory (ReRAM). In this model, the properties of conductive filament control the reliability characteristics. A ReRAM based neural-network processor is also demonstrated. Using well-controlled analog currents, we realized MNIST handwritten digits dataset recognition with low power. Furthermore, the difference in handling reliability for digital memory and analog NN processor is discussed. We propose an NN simulation based on ReRAM reliability model in order to consider the reliability of analog NN processor.

This paper presents low-power neural-network (NN) processor using ReRAM to store weights as analog resistance for future AI computing. We propose ReRAM perceptron circuit for realizing large scale integration, highly accurate cell current controlled writing scheme, and flexible network architecture (FNA) in which any NNs can be configured. Fabricated 180nm test chip shows well-controlled analog cell current with linear 30μA dynamic range and 0.59μA variation of 1 sigma, results in 90.8% MNIST numerical recognition rate. Furthermore, 4M synapses integrated 40nm test chip achieves lower analog cell current and 66.5 TOPS/W power efficiency.

We have developed 40nm ReRAM for low-power embedded applications. Using resistive switching element process technologies and filament characterization methods to realize good switching characteristics, highly reliable 8M-bit 40nm ReRAM array characteristics were obtained in a mass production line. Endurance of 100k cycles and over 10 years' retention at 85 ˚C after 10k cycles were demonstrated. The potential to widen the range of ReRAM applications, such as their use in analog neuromorphic devices for low-power neural network processors and hydrogen sensors based on ReRAM technology, are also described.

This paper presents a secure application—a physically unclonable function (PUF)—that uses the physical property of resistive random access memory (ReRAM). The proposed PUF-generating method and reproducing algorithm achieves highly reliable with bit error rate (BER) < 0.5% and reproduction exceeding 1010 times at −40 to 125°C after 10 years at 125°C and high uniqueness as evidenced by passing NIST tests. Evaluations on 40nm ReRAM test chips have demonstrated the feasibility of a scaled-down ReRAM cell enhanced with PUF.