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A 10-V programmable Josephson voltage standard (PJVS) circuit including 524 288 vertically stacked NbN/TiN/NbN Josephson junctions was successfully fabricated without any defects. The chip was cooled with a compact cryocooler at a temperature of 9.8 K and generated an output voltage of 17.3 V with the first Shapiro step height of 1.0 mA under microwave irradiation at 16 GHz. Furthermore, the circuit design having the high output voltage increased the number of available chips for the 10-V PJVS. The fabrication yield for the chip, which generates greater than 10 V, was 36%, which is ten times greater than that for a perfect chip without any defects. This method was not effective for the chip that had serious defects, such as a disconnection across the array or short between the array and ground; thus, efforts to reduce such defects, e.g., frequent maintenance inside vacuum chambers for film preparation and etching, were found to be essential. [ABSTRACT FROM AUTHOR]

We precisely evaluated a single-chip 10-V programmable Josephson voltage standard (PJVS) system based on a closed-cycle refrigerator by directly comparing it with a conventional Josephson voltage standard system. The PJVS chip fabricated using NbN/TiNx/NbN junction technology was used. The result of the measurement showed a good agreement with a combined standard uncertainty of 3.1 parts in 1010 at 10 V. [ABSTRACT FROM AUTHOR]

Stacked (NbN/TiNX)N/NbN (N = 2, 3, 4, 5 and 10) Josephson junctions and their arrays have been fabricated on a Si chip and their microwave-induced characteristics were measured at a temperature around 10 K. To achieve a vertical and smooth edge of an NbN - TiNX multilayer, an inductively coupled plasma reactive ion etching (ICP-RIE) technique was used. Current-voltage characteristics measured for stacks of (NbN/TiNX)N/NbN Josephson junctions without microwave indicated that critical currents for those junctions distribute in a certain range. We defined Ic - spread as (Ic MAX - Ic MIN)/Ic Average to measure the distribution of Ic. The Ic, - spread was minimized when the thickness of intermediate electrodes was d = 50 nm. We also evaluated values of Ic - spread for stacks prepared at different fabrication runs as a function of the number of junctions in a stack N. As a result, we found N = 3 is the maximum for practical use. For arrays, we obtained a constant-voltage step height of about 2 mA for 2048 stacks of double-barrier junctions (N = 2), and about 1 mA for 1 024 stacks of triple-barrier junctions (N = 3). [ABSTRACT FROM AUTHOR]

We developed a 10-V dc programmable Josephson voltage standard (PJVS) using a multichip technique. The PJVS was based on NbN/TiNx /NbN junctions and operated using a 10-K compact cryocooler. We carried out an indirect comparison with a superconductor-insulator-superconductor-based conventional Josephson voltage standard (JVS) by measuring the voltage of a 10-V zener diode reference standard. The combined standard uncertainty of the comparison was uc = 0.03 μV(k = 1), and the relative combined standard uncertainty was 3 × 10-9. [ABSTRACT FROM AUTHOR]

We evaluated timing jitter based on a time-to-digital converter (TDC) having sub-pico seconds time resolution. The measured jitter at liquid helium temperature was 65 fs for an optimally damped simple junction composing a conventional Josephson transmission line fabricated with the NEC standard process. The temperature dependence and shunt resistance dependence of jitter indicate that the jitter originates from thermal noise generated at the shunt resistor of the junction. We also found that the timing jitter of a balanced comparator is much larger than that of a JTL. The jitter of a balanced comparator is independent of temperature. This means that the jitter of a balanced comparator does not arise from thermal noise. [ABSTRACT FROM AUTHOR]