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Your search keyword '"TAOUIL, MOTTAQIALLAH"' showing total 34 results
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34 results on '"TAOUIL, MOTTAQIALLAH"'

1. Memristor-Based Lightweight Encryption

Author

Siddiqi, Muhammad Ali, Hernández, Jan Andrés Galvan, Gebregiorgis, Anteneh, Bishnoi, Rajendra, Strydis, Christos, Hamdioui, Said, and Taouil, Mottaqiallah

Subjects
Computer Science - Cryptography and Security, Computer Science - Hardware Architecture, Computer Science - Emerging Technologies
Abstract

Next-generation personalized healthcare devices are undergoing extreme miniaturization in order to improve user acceptability. However, such developments make it difficult to incorporate cryptographic primitives using available target technologies since these algorithms are notorious for their energy consumption. Besides, strengthening these schemes against side-channel attacks further adds to the device overheads. Therefore, viable alternatives among emerging technologies are being sought. In this work, we investigate the possibility of using memristors for implementing lightweight encryption. We propose a 40-nm RRAM-based GIFT-cipher implementation using a 1T1R configuration with promising results; it exhibits roughly half the energy consumption of a CMOS-only implementation. More importantly, its non-volatile and reconfigurable substitution boxes offer an energy-efficient protection mechanism against side-channel attacks. The complete cipher takes 0.0034 mm$^2$ of area, and encrypting a 128-bit block consumes a mere 242 pJ.

Published
2024
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2. On BTI Aging Rejuvenation in Memory Address Decoders

Author

Gursoy, Cemil Cem, Kraak, Daniel, Ahmed, Foisal, Taouil, Mottaqiallah, Jenihhin, Maksim, and Hamdioui, Said

Subjects
Computer Science - Hardware Architecture
Abstract

Memory designs require timing margins to compensate for aging and fabrication process variations. With technology downscaling, aging mechanisms became more apparent, and larger margins are considered necessary. This, in return, means a larger area requirement and lower performance for the memory. Bias Temperature Instability (BTI) is one of the main contributors to aging, which slows down transistors and ultimately causes permanent faults. In this paper, first, we propose a low-cost aging mitigation scheme, which can be applied to existing hardware to mitigate aging on memory address decoder logic. We mitigate the BTI effect on critical transistors by applying a rejuvenation workload to the memory. Such an auxiliary workload is executed periodically to rejuvenate transistors that are located on critical paths of the address decoder. Second, we analyze workloads' efficiency to optimize the mitigation scheme. Experimental results performed with realistic benchmarks demonstrate several-times lifetime extension with a negligible execution overhead., Comment: 2022 IEEE 23rd Latin American Test Symposium (LATS)

Published
2022

4. Survey on Architectural Attacks: A Unified Classification and Attack Model

Author

Ghasempouri, Tara, Raik, Jaan, Reinbrecht, Cezar, Hamdioui, Said, and Taouil, Mottaqiallah

Subjects
Computer Science - Cryptography and Security
Abstract

According to the World Economic Forum, cyber attacks are considered as one of the most important sources of risk to companies and institutions worldwide. Attacks can target the network, software, and/or hardware. During the past years, much knowledge has been developed to understand and mitigate cyberattacks. However, new threats have appeared in recent years regarding software attacks that exploit hardware vulnerabilities. We define these attacks as architectural attacks. Today, both industry and academy have only limited comprehension of architectural attacks, which represents a critical issue for the design of future systems. To this end, this work proposes a new taxonomy, a new attack model, and a complete survey of existing architectural attacks. As a result, our study provides the tools to understand the Architectural Attacks deeply and start building better designs as well as protection mechanisms.

Published
2022

11. Memristor-Based Lightweight Encryption

Author

Siddiqi, Muhammad Ali, primary, Galvan Hernández, Jan Andrés, additional, Gebreziorgis, Anteneh, additional, Bishnoi, Rajendra, additional, Strydis, Christos, additional, Hamdioui, Said, additional, and Taouil, Mottaqiallah, additional

Published
2023
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20. ETS 2022 ORGANIZING COMMITTEE

Author

Manich Bou, Salvador, Rodríguez Montañés, Rosa, Bernardi, Paolo, Tille, Daniel, Mir, Salvador, Bosio, Alberto, Arumi Delgado, Daniel, Gómez Pau, Álvaro, Cassano, Luca, Jiao, Hailong, Miclea, Liviu, Sanchez, Ernesto, Savino, Alessandro, Canal Corretger, Ramon, Eggersglüß, Stephan, Fransi, Sergi, Taouil, Mottaqiallah, Calomarde Palomino, Antonio, Weiner, Michael, Michael, Maria K., Sonza Reorda, Matteo, Larsson, Erik, Vatajelu, Elena-Ioana, Stratigopoulos, Haralampos-G., Parisi Baradad, Vicenç, Huang, Junlin, Li, Huawei, Chillarige, Sameer, Kameyama, Shuichi, Carro, Luigi, Su, Fei, Nicolici, Nicola, Huang, Shi-Yu, Manich Bou, Salvador, Rodríguez Montañés, Rosa, Bernardi, Paolo, Tille, Daniel, Mir, Salvador, Bosio, Alberto, Arumi Delgado, Daniel, Gómez Pau, Álvaro, Cassano, Luca, Jiao, Hailong, Miclea, Liviu, Sanchez, Ernesto, Savino, Alessandro, Canal Corretger, Ramon, Eggersglüß, Stephan, Fransi, Sergi, Taouil, Mottaqiallah, Calomarde Palomino, Antonio, Weiner, Michael, Michael, Maria K., Sonza Reorda, Matteo, Larsson, Erik, Vatajelu, Elena-Ioana, Stratigopoulos, Haralampos-G., Parisi Baradad, Vicenç, Huang, Junlin, Li, Huawei, Chillarige, Sameer, Kameyama, Shuichi, Carro, Luigi, Su, Fei, Nicolici, Nicola, and Huang, Shi-Yu

Published
2022

21. S8 - PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

Author

Fieback, Moritz, Münch, Christopher, Gebregiorgis, Anteneh, Cardoso Medeiros, Guilherme, Taouil, Mottaqiallah, Hamdioui, Said, Tahoori, Mehdi, Fieback, Moritz, Münch, Christopher, Gebregiorgis, Anteneh, Cardoso Medeiros, Guilherme, Taouil, Mottaqiallah, Hamdioui, Said, and Tahoori, Mehdi

Abstract

Emerging non-volatile resistive memories like Spin- Transfer Torque Magnetic Random Access Memory (STTMRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in highperformance CiM, while RRAM is used for edge CiM.

Published
2022

22. POS2 - Smart Redundancy Schemes for ANNs Against Fault Attacks

Author

Köylü, Troya Çagıl, Hamdioui, Said, Taouil, Mottaqiallah, Köylü, Troya Çagıl, Hamdioui, Said, and Taouil, Mottaqiallah

Abstract

Artificial neural networks (ANNs) are used to accomplish a variety of tasks, including safety critical ones. Hence, it is important to protect them against faults that can influence decisions during operation. In this paper, we propose smart and low-cost redundancy schemes that protect the most vulnerable ANN parts against fault attacks. Experimental results show that the two proposed smart schemes perform similarly to dual modular redundancy (DMR) at a much lower cost, generally improve on the state of the art, and reach protection levels in the range of 93% to 99%.

Published
2022

32. Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation

Author

Aziza, Hassen, Hamdioui, Said, Fieback, Moritz, Taouil, Mottaqiallah, Moreau, Mathieu, Girard, Patrick, Virazel, Arnaud, Coulié, Karine, Institut des Matériaux, de Microélectronique et des Nanosciences de Provence (IM2NP), Aix Marseille Université (AMU)-Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS), Aix Marseille Université (AMU), Delft University of Technology (TU Delft), Test and dEpendability of microelectronic integrated SysTems (TEST), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Université de Toulon (UTLN)-Centre National de la Recherche Scientifique (CNRS)-Aix Marseille Université (AMU), HORIBA France SAS [Villeneuve d'Ascq], HORIBA Scientific [France], TEST (TEST), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
010302 applied physics, Multi-level cell, Cost structure, Computer science, variability, current control, 02 engineering and technology, Hafnium compounds, 01 natural sciences, RRAM, Die (integrated circuit), Resistive random-access memory, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, 020201 artificial intelligence & image processing, OxRAM multi-level cell, write termination, QLC, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Reset (computing), ComputingMilieux_MISCELLANEOUS, MLC
Abstract

International audience; Multi-Level Cell (MLC) technology can greatly reduce Resistive RAM (RRAM) die sizes to achieve a breakthrough in cost structure. In this paper, a novel design scheme is proposed to realize reliable and uniform MLC RRAM operation without the need of any read verification. MLC is implemented based on a strict control of the cell programming currents of 1T-1R HfO 2 -based RRAM cells. Specifically, a self-adaptive write termination circuit is proposed to control the RRAM RESET current. Eight different resistance states are obtained by varying the compliance current which is defined as the minimal current allowed by the termination circuit in the RESET direction.

Published
2021

34. Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs.

Author

Wu, Lizhou, Rao, Siddharth, Taouil, Mottaqiallah, Marinissen, Erik Jan, Kar, Gouri Sankar, and Hamdioui, Said

Subjects
MAGNETIC tunnelling, MANUFACTURING processes
Abstract

The manufacturing process of STT-MRAM requires unique steps to fabricate and integrate magnetic tunnel junction (MTJ) devices which are data-storing elements. Thus, understanding the defects in MTJs and their faulty behaviors are paramount for developing high-quality test solutions. This article applies the advanced device-aware test to intermediate (IM) state defects in MTJ devices based on silicon measurements and circuit simulations. An IM state manifests itself as an abnormal third resistive state, which differs from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60nm to 120nm; the results show that the occurrence probability of IM state strongly depends on the switching direction, device size, and bias voltage. We demonstrate that the conventional resistor-based fault modeling and test approach fails to appropriately model and test such a defect. Therefore, device-aware test is applied. We first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, this model is used for a systematic fault analysis based on circuit simulations to obtain accurate and realistic faults in a pre-defined fault space. Our simulation results show that an IM state defect leads to intermittent write transition faults. Finally, we propose and implement a device-aware test solution to detect the IM state defect. [ABSTRACT FROM AUTHOR]

Published
2022
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