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Soft errors are the most common aspect of errors that are incurred in the memory devices during transmission. The common and fundamental reason of these soft errors is radiation that produces leakage of current and results in misleading information which is sent to various transmission stations via satellite and microwave communication. In this paper, the real-time embedded system is designed and implemented to mitigate the soft error using hybrid Hamming code. The work also develops the hardware system for soft error mitigation. The designed system is compared with the other coding schemes that are commonly available for error mitigation. The performance of real-time embedded system for soft error mitigation is carried out using signal-to-noise ratio and other performance metrics. The timing diagram analysis is the key metrics of the paper that defined the performance of the designed soft error mitigation design using the proposed technique. Furthermore, the results of the designed systems are demonstrated using bit error probability, Pb and channel symbol error probability (CSEP). The impact of the designed system will be that from now onwards using the proposed system, the soft error produced due to radiation and other reasons would not affect too much on transmission and reception of important data via satellite and microwave communication. [ABSTRACT FROM AUTHOR]

Arsenic exposure through drinking water is a serious public health concern in the southern province of Pakistan. Little information on As exposure to children at school settings is available in Pakistan. The current study aimed to assess arsenic contamination through drinking water sources and estimate its health risk to the children, the potentially malnourished Pakistan population. We used risk assessment models to estimate the hazard quotient index and lifetime cancer risk. Spatial data analysis methods were used to investigate the spatial pattern of As contamination and its relationship with the area's hydrogeology. Across the 423 sampled schools, the drinking water exceeded the WHO permissible limits (19.6% for arsenic and 15% for iron). The arsenic's average incremental lifetime cancer risk (ILCR) exceeded the USEPA permissible limit. The arsenic hotspots were mainly located in the central districts. The present study's findings elaborate that the reduction is the controlling phenomenon in the lower Indus basin in the active flood plains, which is the primary source of fresh groundwater in Sindh and pH-induced dissolution is the second phenomenon observed only in the irrigated area, especially at the boundary of the hotspots. These findings are helpful to inform policymakers on measures to ensure prior treatment of As in the drinking water for the schools in areas adjacent to the riverbank. [ABSTRACT FROM AUTHOR]

It is discussed in many studies and demonstrated in many pieces of research that based on certain applications, analog design of filter has several issues including complex design, re-use limitations, and accuracy of generating the output at various frequencies. Therefore, instead of analog filter design, the digital design of the filter is preferred for both Finite and Infinite Impulse Response Filter. This paper demonstrates the design of the digital Finite Impulse Response (FIR) filter designed is demonstrated using Ultra-Scale Field Programming Gate Array (FPGA) having chip XCKU3P. The filter is designed using a coefficient multiplier via Canonic Signed Digit (CSD) Technique. The optimized design of the digital filter is conducted via real-time implementation is performed using Ultra-Scale FPGA. The filter is designed and evaluated with an ordinary filter at 10 MHz and 10 GHz frequencies. The performance analysis of the system is illustrated using the response rate at the bitstream of 16-bit. In the results, it is demonstrated that for 10 MHz frequency design FIR filter in FPGA the 30% faster response filter is achieved at for 10 GHz, the 15% faster response is achieved at the I/O standard of Low Voltage Complementary Metal Oxide Semiconductor (LVCOMS). The optimization of 30% in terms of the response time of the filter is attained using the proposed work. The proposed improved FIR filter design using Ultra-Scale FPGA helps in increasing design performance to increase the speed of overall response of FIR filter that is lacking in ordinary Filters. [ABSTRACT FROM AUTHOR]