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1. True Random Number Generator Based on RRAM-Bias Current Starved Ring Oscillator

Author

D. Arumi, S. Manich, A. Gomez-Pau, R. Rodriguez-Montanes, M. B. Gonzalez, and F. Campabadal

Subjects
Hardware security, non-volatile memory (NVM), random number generation, ring oscillator, resistive random access memory (RRAM), true random number generator (TRNG), Computer engineering. Computer hardware, TK7885-7895
Abstract

This work presents a resistive random access memory (RRAM)-bias current-starved ring oscillator (CSRO) as true random number generator (TRNG), where the cycle-to-cycle variability of an RRAM device is exploited as source of randomness. A simple voltage divider composed of this RRAM and a resistor is considered to bias the gate terminal of the extra transistor of every current starved (CS) inverter of the ring oscillator (RO). In this way, the delay of the inverters is modified, deriving an unpredictable oscillation frequency every time the RRAM switches to the high resistance state (HRS). The oscillation frequency is finally leveraged to extract the sequence of random bits. The design is simple and adds low area overhead. Experimental measurements are performed to analyze the cycle-to-cycle variability in the HRS. The very same measurements are subsequently used to validate the TRNG by means of electrical simulations. The obtained results passed all the National Institute of Standards and Technology randomness tests (NIST) tests without the need for postprocessing.

Published
2023
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2. On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data

Author

V. Mahboubi, D. Arumi, A. Gomez, R. Rodriguez, S. Manich, Universitat Politècnica de Catalunya. Doctorat en Enginyeria Electrònica, and Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica

Subjects
Compact model, Integrated circuits, Verilog-A, Enginyeria electrònica::Microelectrònica::Circuits integrats [Àrees temàtiques de la UPC], Circuits integrats, Memristor, RRAM
Abstract

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The use of Resistive Random Access Memory (RRAM) devices is becoming pervasive in many applications. In particular, security based primitives can exploit their variability and non-volatility for generating cells for Non-Volatile Secure Memory (NVSM) and Physically Unclonable Function (PUF). Stanford-PKU Resistive Random Access Memory (RRAM) model is a successful model that has been used for simulating different types of RRAM-based systems. However, some circuit-related problems appear when more than one device are coupled together. In this paper, a parameter fitting is performed for a real TiN/Ti/HfO 2 /W RRAMs and the statistical characteristics of the variability in the experimental data are analyzed and included in order to obtain a more reliable model for simulations. This work was supported in part by the Spanish Ministry of Science, Innovation and Universities under Grant PID2019-103869RB-C33/ AEI /10.13039/501100011033, and through FEDER funds under Grant TEC2017- 84321-C4-1-R. Peer Reviewed Objectius de Desenvolupament Sostenible::9 - Indústria, Innovació i Infraestructura

Published
2022
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