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Two-dimensional materials (2DMs) have been widely investigated because of their potential for heterogeneous integration with modern electronics. However, several major challenges remain, such as the deposition of high-quality dielectrics on 2DMs and the tuning of the 2DM doping levels. Here, we report a scalable plasma-enhanced atomic layer deposition (PEALD) process for direct deposition of a nonstoichiometric aluminum oxide (AlOX) dielectric, overcoming the damage issues associated with conventional methods. Furthermore, we control the thickness of the dielectric layer to systematically tune the doping level of 2DMs. The experimental results demonstrate successful deposition without detectable damage, as confirmed by Raman spectroscopy and electrical measurements. Our method enables tuning of the Dirac and threshold voltages of back-gated graphene and MoS${_2}$ field-effect transistors (FETs), respectively, while also increasing the charge carrier mobility in both device types. We further demonstrate the method in top-gated MoS${_2}$ FETs with double-stack dielectric layers (AlOX+Al${_2}$O${_3}$), achieving critical breakdown field strengths of 7 MV/cm and improved mobility compared with the back gate configuration. In summary, we present a PEALD process that offers a scalable and low-damage solution for dielectric deposition on 2DMs, opening new possibilities for precise tuning of device characteristics in heterogeneous electronic circuits., Comment: 28 pages

Graphene is a promising material for applications as a channel in graphene field-effect transistors (GFETs) which may be used as a building block for optoelectronics, high-frequency devices and sensors. However, these devices require gate insulators which ideally should form atomically flat interfaces with graphene and at the same time contain small densities of traps to maintain high device stability. Previously used amorphous oxides, such as SiO2 and Al2O3, however, typically suffer from oxide dangling bonds at the interface, high surface roughness and numerous border oxide traps. In order to address these challenges, here we use for the first time 2nm thick epitaxial CaF2 as a gate insulator in GFETs. By analyzing device-to-device variability for over 200 devices fabricated in two batches, we find that tens of them show similar gate transfer characteristics. Our statistical analysis of the hysteresis up to 175C has revealed that while an ambient-sensitive counterclockwise hysteresis can be present in some devices, the dominant mechanism is thermally activated charge trapping by border defects in CaF2 which results in the conventional clockwise hysteresis. We demonstrate that both the hysteresis and bias-temperature instabilities in our GFETs with CaF2 are comparable to similar devices with SiO2 and Al2O3. In particular, we achieve a small hysteresis below 0.01 V for equivalent oxide thickness (EOT) of about 1 nm at the electric fields up to 15 MV/cm and sweep times in the kilosecond range. Thus, our results demonstrate that crystalline CaF2 is a promising insulator for highly-stable GFETs.

Intensive research is carried out on two-dimensional materials, in particular molybdenum disulfide, towards high-performance transistors for integrated circuits. Fabricating transistors with ohmic contacts is challenging due to the high Schottky barrier that severely limits the transistors' performance. Graphene-based heterostructures can be used in addition or as a substitute for unsuitable metals. We present lateral heterostructure transistors made of scalable chemical vapor-deposited molybdenum disulfide and chemical vapor-deposited graphene with low contact resistances of about 9 k${\Omega}$${\mu}$m and high on/off current ratios of 10${^8}$. We also present a theoretical model calibrated on our experiments showing further potential for scaling transistors and contact areas into the few nanometers range and the possibility of a strong performance enhancement by means of layer optimizations that would make transistors promising for use in future logic circuits., Comment: 39 pages

A 200 mm processing platform for the large-scale production of graphene field-effect transistor-quantum dot (GFET-QD) hybrid photodetectors is demonstrated. Comprehensive statistical analysis of electric data shows a high yield (96%) and low variation of the 200 mm scale fabrication. The GFET-QD devices deliver responsivities of 10${^5}$ - 10${^6}$ V/W in a wavelength range from 400 to 1800 nm, at up to 100 frames per second. Spectral sensitivity compares well to that obtained using similar GFET-QD photodetectors. The device concept enables gate-tunable suppression or enhancement of the photovoltage, which may be exploited for electric shutter operation by toggling between the signal capture and shutter states. The devices show good stability at a wide operation range and external quantum efficiency of 20% in the short-wavelength infrared range. Furthermore, an integration solution with complementary metal-oxide-semiconductor technology is presented to realize image-sensor-array chips and a proof-of-concept image system. This work demonstrates the potential for the volume manufacture of infrared photodetectors for a wide range of imaging applications., Comment: 29 pages

The deposition of dielectric materials on graphene is one of the bottlenecks for unlocking the potential of graphene in electronic applications. In this paper we demonstrate the plasma enhanced atomic layer deposition of 10 nm thin high quality Al$_2$O$_3$ on graphene using a monolayer of hBN as protection layer. Raman spectroscopy was performed to analyze possible structural changes of the graphene lattice caused by the plasma deposition. The results show that a monolayer of hBN in combination with an optimized deposition process can effectively protect graphene from damage, while significant damage was observed without an hBN layer. Electrical characterization of double gated graphene field effect devices confirms that the graphene did not degrade during the plasma deposition of Al$_2$O$_3$. The leakage current densities were consistently below 1 nA/mm for electric fields across the insulators of up to 8 MV/cm, with irreversible breakdown happening above. Such breakdown electric fields are typical for Al$_2$O$_3$ and can be seen as an indicator for high quality dielectric films.

We demonstrate the design, fabrication, and characterization of wafer-scale, zero-bias power detectors based on two-dimensional MoS$_2$ field effect transistors (FETs). The MoS$_2$ FETs are fabricated using a wafer-scale process on 8 $\mu$m thick polyimide film, which in principle serves as flexible substrate. The performances of two CVD-MoS$_2$ sheets, grown with different processes and showing different thicknesses, are analyzed and compared from the single device fabrication and characterization steps to the circuit level. The power detector prototypes exploit the nonlinearity of the transistors above the cut-off frequency of the devices. The proposed detectors are designed employing a transistor model based on measurement results. The fabricated circuits operate in Ku-band between 12 and 18 GHz, with a demonstrated voltage responsivity of 45 V/W at 18 GHz in the case of monolayer MoS2 and 104 V/W at 16 GHz in the case of multilayer MoS$_2$, both achieved without applied DC bias. They are the best performing power detectors fabricated on flexible substrate reported to date. The measured dynamic range exceeds 30 dB outperforming other semiconductor technologies like silicon complementary metal oxide semiconductor (CMOS) circuits and GaAs Schottky diodes., Comment: 28 pages

PtSe$_2$ is one of the most promising materials for the next generation of piezoresistive sensors. However, the large-scale synthesis of homogeneous thin films with reproducible electromechanical properties is challenging due to polycrystallinity. We show that stacking phases other than the AA-stacking in the 1T phase become thermodynamically available at elevated temperatures. We show that these can make up a significant fraction in a polycrystalline thin film and discuss methods to characterize these stacking phases. Lastly, we estimate their gauge factors, which vary strongly and significantly impact the performance of a nanoelectromechanical device.