19 results on '"Gai, Weixin"'
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2. 56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology
3. The Impact of CTLE Poles on Receiver Eye Diagrams
4. A Dual-Core Digitally Controlled Oscillator with a Switched Capacitor
5. Adaptive Resistance Calibration Circuit for High-speed Serial Transceivers
6. A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS
7. 6.7 A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS
8. 6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS
9. A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS
10. A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS
11. A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS
12. A Delay Matching Technique for Relative Deterministic Jitter Reduction in 28GHz ADPLL
13. An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC
14. A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver
15. A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications
16. Closed-Loop Diabetes Minipatch Based on a Biosensor and an Electroosmotic Pump on Hollow Biodegradable Microneedles
17. A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS
18. A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS
19. An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology
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