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Cryptography hardware is vulnerable to side-channel (SC) attacks on power supply current flow and electromagnetic (EM) emission. This article proposes simulation-based power and EM side-channel leakage analysis (SCLA) techniques on a cryptographic integrated circuit (IC) chip in system level assembly. SCLA measures SC leakage metrics including T-score, SC leakage score, and the number of measurement traces to disclosure, leveraged by a secure system-on-chip design flow toward SC attack resiliency and SC leakage sign off. Power SCLA features the tracking of security sensitive registers within cryptographic logic paths and the automatic assignments of probe points on associated physical power nets. Power supply current traces are efficiently simulated for the large set of input payloads, with direct vector-based and vector-less random switching controls. EM SCLA evaluates magnetic fields created by every piece of metal wiring in metal stacks where power supply current of cryptographic processing flows. The EM emission and EM SCLA from the backside Si surface of an IC chip in flip-chip packaging are experimentally examined with a 0.13 µm test chip. The proposed simulation-based SCLA exhibits the SC leakage metrics of on-chip location and direction dependency as accurately as in the measurements. [ABSTRACT FROM AUTHOR]

Gallium Oxide (Ga 2 O 3) holds significant potential for the next generation of electronic devices following SiC and GaN due to its ultra-wide bandgap of approximately 4.5 eV - 4.9 eV and high theoretical critical breakdown field strength of 8 MV/cm. Nonetheless, Ga 2 O 3 has a naturally low thermal conductivity, resulting in limited device output performance and hindering Ga 2 O 3 devices from reaching their full theoretical potential. In this study, we demonstrate that the appropriate thermal management strategy can solve the above challenges. By comparing the thermal control schemes including the Ga 2 O 3 FET devices on the original substrate, the thinned Ga 2 O 3 substrate, the high thermal conductivity substrate, the heat sink packaging, and the flip-chip packaging, it is demonstrated that the flip-chip model is the most effective strategy to improve the heat dissipation performance of the Ga 2 O 3 device. By utilizing the appropriate carrier in flip-chip packaging, the temperature elevation of the device at 2 W/mm power density will be diminished by around 91% in contrast to the initial basic device. Furthermore, the output performance of the device demonstrates significant enhancement. This thermal management technique successfully resolves the severe heat dissipation issue prevalent in Ga 2 O 3 devices and eliminates primary obstacles concerning the industrialization of Ga 2 O 3 RF and power devices. • Establishing a thermoelectric coupling model to solve the problem of Ga 2 O 3 transistor thermal management. • Replacing the native substrate is not an optimal solution to the thermal problem of Ga 2 O 3 transistors. • The chip flip packaging can greatly improve the heat dissipation performance of Ga 2 O 3 devices. [ABSTRACT FROM AUTHOR]