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Synchronously sampling three-phase current in the traction control unit based on the control cycle is necessary to enhance control of permanent magnet synchronous motors. Simultaneously, continuous current sampling at small time intervals is essential for realtime over-current protection. This paper presents a solution based on a field-programmable gate array (FPGA), which incorporates a single set of analog-to-digital converter (ADC) chips to enable both synchronous current sampling essential for controlling permanent magnet synchronous motors and fast timed sampling necessary for real-time over-current protection. This design intelligently generates ADC conversion start signals through acquiring user-configured synchronous sampling periods in real time alongside timed sampling periods, thus enabling synchronous and timed current sampling control for permanent magnet synchronous motors. Finally, experiments were conducted on an actual permanent magnet traction control platform to verify the feasibility and effectiveness of the proposed scheme.

Copyright of Journal of Data Acquisition & Processing / Shu Ju Cai Ji Yu Chu Li is the property of Editorial Department of Journal of Nanjing University of Aeronautics & Astronautics and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Aiming at the position control problem of a 7 degree of freedom (7 DOF) manipulator in the presence of model uncertainty and unknown external disturbances such as friction and gravity, a 7 DOF manipulator driving integrated controller was developed. Firstly, a 7 DOF robotic arm drive control based on advanced risc machines (ARM) + digital signal processor (DSP) + field programmable gate array (FPGA) architecture was designed. The integrated controller scheme was ensured sufficient computing performance. Secondly, a 7 DOF manipulator multi-motor cooperative control method was proposed to improve the accuracy and stability of the manipulator position control system. Then, a nonlinear disturbance observer and the composite control law of the fast-continuous non-singular terminal synovium was used to compensate for external disturbances and system uncertainty, while ensuring the rapid convergence of the system. Finally, the experiments of the position control, speed control, constant torque control and sliding mode position control based on nonlinear disturbance observer were carried out. The effectiveness of the driving integrated control scheme and the composite control strategy was verified. The research results show that the adopted drive-control integrated controller and multi-motor position synergistic control method can ensure that the steady-state error of the position, speed and constant torque control of the joint motor of the 7 DOF manipulator is within 1%. The design based on nonlinear disturbance observer compared with the proportional integral derivative (PID) position control, the performance of overshoot, response speed and steady-state accuracy are improved by 10%～15%. It meets the requirements of high-speed and high-precision servo control of the robotic arm. [ABSTRACT FROM AUTHOR]

Aiming at the problem of non-linearity between desired output and the input of a proportional solenoid valve amplifier without external feedback signal, the function of each parameter in the operation of the amplifier was studied, and a method to implement a linear amplifier by pre-storing matching parameters and executing no tracking during current jump was proposed. Firstly, the problems that need to be solved effectively in realizing linear amplifier were defined. Secondly, based on those problems, through analysis of the existing amplifiers using TRIZ, the solution of inventive principles was obtained. Then, according to the solution, the control value-output current relationship was formed into an inverse matching table, the output current-sampling current relationship was formed into another matching table, and the two matching tables were pre-stored in the amplifier. Finally, the control functions of the amplifier were realized in field programmable gate array (FPGA), and the measurement of matching parameters, test of static performance of the amplifier, and verification of engineering application were carried out for different proportional valves. The research results show that the implementation of the digital linear amplifier is reasonable and effective, with linear error between the input/output less than 1.5%and the current steady-state establishment time less than 0.1 s. The amplifier can be applied in the hydraulic system, reducing complexity of its control system. The control system can exchange parameters with the amplifier on time, which is convenient for remote control. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In the automatic analysis of retinal images, the location of optic disc and macula fovea is a prerequisite for computer aided diagnosis or screening of diabetic retinopathy. In this paper, a novel algorithm for locating the optic disc and macula fovea in retinal images based on YOLOv4-tiny is proposed and transplanted to field programmable gate array (FPGA) platform. Compared with the traditional method, the present work can not only locate the position of the disc and macula in retinal images simultaneously, quickly and precisely, but also be the first attempt to realize 38 layers mediumsized neural network through using high level synthesis (HLS) language and time division multiplexing technology. The COCO data set and 381 retinal images from the recognized Kaggle-Diabetic Retinopathy Detection competition are used in the training experiment. From the experimental results, the mean average precision (mAP) of optic disc and macular fovea localization after transplanting to FPGA platform is 96.11%, and it only takes 150.445 ms to detect an image on the FPGA system, which presents a good clinical application prospect in related fields. [ABSTRACT FROM AUTHOR]

In recent years, traditional computer architectures have gradually been faced with severe bottlenecks of "Memory Wall" and "Power Wall", with the step-down Moore􀆳s law. However, many other new forms of computing paradigms and computer architectures have been proposed, including neuromorphic computing. Given the characteristic of computing in memory, neuromorphic computing plays a vital role in breaking down the limitation caused by both "Memory Wall" and "Power Wall" constraints in Von Neumann architecture. Many neuromorphic applications on neuromorphic processors have already been demonstrated as high efficiency and accuracy. Currently, in the application scenarios of large-scale biological neural networks, it is necessary to improve the scalability of multi-core neuromorphic processors and maintain their high data throughput and low transmission delay. Today, most multi-core neuromorphic processors adopt a network-on-chip (NoC) as the interconnect structure. However, there are still relatively few verification studies on such NoC. Given the importance of NoC in designing a neuromorphic processors, it is quite necessary to set up a complete and robust NoC functional verification platform for neuromorphic processors. The purpose of this paper is to generate the stimulus files required for behavioral and FPGA hardware-level testing based on the randomization method, and to achieve a more comprehensive functional verification through efficient processing of log files. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)