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Proportion Integration Differentiation (PID) is a common clock disciplining algorithm. In satellite clock source equipment and in Internet of Things (IoT) sensor nodes it is usually required that both time and frequency signals have high accuracy. Because the traditional PID clock disciplining method used in the equipment only performs PID calculation and feedback control on single variable, such as frequency, the time accuracy error of the clock source is large and even has inherent deviation. By using the integral relationship between frequency and time, a new two variables PID control algorithm for high-precision clock disciplining is proposed in this paper. Time is taken as the constraint variable to make the time deviation converge. It can guarantee a high accuracy of time and high long-term stability of frequency. At the same time, frequency is taken as the feedback variable to make frequency obtain fast convergence. It can ensure high short-term stability of the frequency and the continuity of time. So, it can make the time and frequency of the disciplined clock have high accuracy and stability at the same time. In order to verify the effectiveness of the proposed algorithm, it is simulated based on the GNSS disciplined clock model. The GNSS time after Kalman filtering is used as the time reference to discipline the local clock. The simulation results show that the time deviation range of a local clock after convergence is −0.38 ns∼0.31 ns, the frequency accuracy is better than 1 × 10 − 15 averaging over one day, and the long-term time stability (TDEV) for a day is about 7 ps when using the two variables PID algorithm. Compared with the single variable PID algorithm, the time accuracy of the two variables PID algorithm is improved by about one order of magnitude and the long-term time stability (TDEV) is improved by about two orders of magnitude. The research results indicate that the two variables PID control algorithm has great application potential for the development of clock source equipment and other bivariate disciplining scenarios. [ABSTRACT FROM AUTHOR]

Marine controlled source electromagnetic (MCSEM) method is widely used to reveal the electrical structure of shallow media below the seafloor. It is an indispensable geophysical means in the exploration of marine oil and gas exploration, natural gas hydrates and seafloor geological structures. The transmitter and receiver in electromagnetic detection equipment need to maintain a high temporal consistency, usually using high-stability pulse-per-second (PPS) generated by GPS or BeiDou navigation modules as a synchronization signal. Coaxial cable is a widely used tow cable, so it is necessary to design a clock synchronization method of marine controlled source electromagnetic transmitter using coaxial cable. This paper proposes a method for synchronizing the internal clocks of the transmitter with PPS using ship-borne power supply when coaxial cable is used as tow cable. In this method, the ship-borne high-power supply outputs a high-voltage AC signal that is synchronized with the 400 Hz signal output from GPS; the coaxial cable transmits AC high power electrical energy and control commands; the AC signal transmitted via the coaxial cable is converted into a stable and continuous 1 Hz signal by step-down, waveform shaping and frequency division for synchronizing the internal time pulses of the transmitter. The test result shows that the 1 Hz signal obtained by this method has a deviation of about 504 ns relative to the PPS. This deviation meets the need of MCSEM transmitter for clock synchronization. [ABSTRACT FROM AUTHOR]

Phase alignment of periodic events between multiple systems is required in multiple fields and applications. Most of the existing solutions focus on either low frequency and relatively low accuracy or high complexity, high accuracy and precision. In contrast, this work aimed to develop an intermediate solution, supporting high frequencies and relatively high accuracy and precision, with relatively low complexity. A hypothetical concept and mathematical model is presented with a hardware test implementation based entirely on FPGA resources. Deliberate resource selection and utilization enables a significant simplification of calculations and, as a result, a reduction in logic resource utilization. The proposed concept was implemented and verified using the AMD/Xilinx Artix 7 35T FPGA platform. [ABSTRACT FROM AUTHOR]

Clock synchronization is critically important in positioning, navigation and timing systems. While its performance has been intensively studied in a wide range of disciplines, much less is known for the fundamental thermodynamics of clock synchronization‒what limits the precision and how to optimize the energy cost for clock synchronization. Here, we report the first experimental investigation of two stochastic autonomous clocks synchronization, unveiling the thermodynamic relation between the entropy cost and clock synchronization in an open cavity optomechanical system. Two interacting clocks are synchronized spontaneously owing to the disparate decay rates of hybrid modes by engineering the controllable cavity-mediated dissipative coupling. The measured dependence of the degree of synchronization on the overall entropy cost exhibits an unexpected non-monotonic characteristic, while the relation between the degree of synchronization and the entropy cost for the synchronization is monotonically decreasing. The investigation of transient dynamics of clock synchronization exposes a trade-off between energy and time consumption. Our results demonstrate the possibility of clock synchronization in an effective linear system, reveal the fundamental relation between clock synchronization and thermodynamics, and have a great potential for precision measurements, distributed quantum networks, and biological science. [ABSTRACT FROM AUTHOR]

The inter-satellite link (ISL) has been received increasing attention, as it is a potential way to achieve autonomous clock synchronization for envisioned space-based satellite networks with minimal ground segment capability. Existing satellite clock synchronization solutions either rely on prior information or modelling the relative motion by an approximated polynomial. In this paper, we propose a deep learning approach based on long short-term memory (LSTM) to decouple the clock parameters from pseudo-range measurements. The process of clock parameter estimation solely relies on the observed pseudo-range measurements, and the prior information of position and velocity are not required and the nonlinear relative motion process is modelled by training on historical data. The simulation results show that the proposed method outperforms the benchmark solutions in terms of accuracy. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock's phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps. [ABSTRACT FROM AUTHOR]

The clock synchronization is a key technology for the reliability of wireless sensor networks (WSN). To reduce the communication burden and address the challenge of clock synchronization for high-precise clock systems in WSN with switching topologies, this paper proposes an event-triggered synchronization strategy for high-precise clock systems. Firstly, based on the concept of offset and skew, the model of whole clock systems is investigated and an event-triggered strategy is proposed for high-precise clock systems with switching topologies. Then, a synchronization strategy for clock systems is presented to achieve clock synchronization with the convergence of clock offset and clock skew. The sufficient condition for the synchronization of high-precise clock systems with switching topologies is obtained. Afterwards, the optimal event-triggered weighting matrices and controller gains are calculated by converting the clock synchronization problem as a solvable optimization problem. Finally, the performance of the proposed clock synchronization method is evaluated by simulations.

With the rapid development of information technology, high-speed digital optical signal transmission technology has become the core of modern communication networks. However, the increase in transmission rates brings challenges such as noise, distortion, and interference, which affect the accuracy of clock recovery. To address these issues, this study proposes a clock recovery algorithm based on the eye diagram opening area to improve the accuracy and efficiency of high-speed digital optical signal jitter measurement. The proposed method extracts clock information from the signal using the opening area and curvature characteristics of the eye diagram for jitter measurement. Experimental results demonstrate that the clock recovery algorithm based on the eye diagram opening area can stably reconstruct the signal eye diagram and obtain jitter parameters under different optical power conditions. At optical powers of −7.2 dBm, −12.2 dBm, and −17.2 dBm, the Q-factors were 8.8, 7.6, and 4.3, respectively, and the RMS jitter values were 12.2 ps, 13.4 ps, and 21.2 ps, respectively. At optical powers of −2.3 dBm, 0.1 dBm, 2.4 dBm, 4.6 dBm, and 6.0 dBm, the Q-factors were 9.1, 9.3, 9.5, 9.7, and 10.0, respectively, and the average jitter values were 8.9 ps, 8.5 ps, 8.0 ps, 7.5 ps, and 7.0 ps. These results indicate that the proposed algorithm performs excellently under low optical power conditions and maintains high recovery accuracy even when jitter increases at higher optical powers. The clock recovery algorithm based on the eye diagram opening area significantly improves the accuracy and stability of high-speed digital optical signal jitter measurement, enriches the theoretical research of clock recovery algorithms, and shows significant advantages in improving signal transmission quality, reducing bit error rate, and enhancing communication link reliability. The research outcomes provide key technical support for the optimization of modern high-speed optical communication systems.

Clock synchronization is one of the popular research topics in Distributed Measurement and Control Systems (DMCSs). In most industrial fields, such as Smart Grid and Flight Test, the highest requirement for synchronization accuracy is 1 μs. IEEE 1588 Precision Time Protocol-2008 (PTPv2) can theoretically achieve sub-microsecond accuracy, but it relies on the assumption that the forward and backward delays of PTP packets are symmetrical. In practice, PTP packets will experience random queue delays in switches, making the above assumption challenging to satisfy and causing poor synchronization accuracy. Although using switches supporting the Transparent Clock (TC) can improve synchronization accuracy, these dedicated switches are generally expensive. This paper designs a PTP clock servo for compensating Queue-Induced Delay Asymmetry (QIDA), which can be implemented based on ordinary switches. Its main algorithm comprises a minimum window filter with drift compensation and a fuzzy proportional–integral (PI) controller. We construct a low-cost hardware platform (the cost of each node is within USD 10) to test the performance of the clock servo. In a 100 Mbps network with background (BG) traffic of less than 70 Mbps, the maximum absolute time error (max |TE|) does not exceed 0.35 μs, and the convergence time is about half a minute. The accuracy is improved hundreds of times compared with other existing clock servos. [ABSTRACT FROM AUTHOR]

The Mössbauer rotor effect recently gained a renewed interest due to the discovery and explanation of an additional effect of clock synchronization which has been missed for about 50 years, i.e. starting from a famous book of Pauli, till some more recent experimental analyses. The theoretical explanation of such an additional effect is due to some recent papers in the general relativistic framework. Here, we show that the additional effect of clock synchronization can be calculated in another way via the third postulate of relativity. [ABSTRACT FROM AUTHOR]

Summary: Given the complexity of current supercomputers and applications, being able to trace application executions to understand their behavior is not a luxury. As constraints, tracing systems have to be as little intrusive as possible in the application code and performances, and be precise enough in the collected data. In this article, we present how works the tracing system used by the task‐based runtime system StarPU. We study the different sources of performance overhead coming from the tracing system and how to reduce these overheads. Then, we evaluate the accuracy of distributed traces with different clock synchronization techniques. Finally, we summarize our experiments and conclusions with the lessons we learned to efficiently trace applications, and the list of characteristics each tracing system should feature to be competitive. The reported experiments and implementation details comprise a feedback of integrating into a task‐based runtime system state‐of‐the‐art techniques to efficiently and precisely trace application executions. We highlight the points every application developer or end‐user should be aware of to seamlessly integrate a tracing system or just trace application executions. [ABSTRACT FROM AUTHOR]

Assessing the motion of moving objects from video footage captured using multiple recording devices requires precise timing and location data, which remains equally important in mobile recording systems. Although capturing high-precision clocks and analyzing these images are effective methods for obtaining accurate time information, a definitive method for precisely determining the capture time from images of rapidly time-varying clocks at various exposure durations is currently lacking. This paper introduces a design method for a dynamic optical marker called the Optical Clock Beacon (OCB), which indicates the current time by integrating multiple point light sources. Our goal is to enable accurate determination of the capture time from images. We present a method for estimating this time using image analysis and validate its accuracy. The simplest OCB configuration translates the binary representation of the current time into a Gray code, with each bit’s state indicated by light sources of positive and negative logic. This approach allows the determination of an image capture time with precision matching of the exposure duration. Furthermore, we outline a design strategy that improves the time accuracy by making the light source configuration of each digit redundant, thus providing substantial design flexibility for the OCB. We also detail the prototype hardware and the image analysis system of the developed OCB, demonstrating through evaluation experiments that the anticipated time accuracy is achievable.

IEEE 1588, also known as the Precision Time Protocol (PTP), is a standard protocol for clock synchronization in distributed systems. While it is not architecture-specific, implementing IEEE 1588 on Reduced Instruction Set Computer-V (RISC-V) low-power embedded devices demands considering the system requirements and available resources. This paper explores various approaches and techniques to achieve accurate time synchronization in such instruments. The analysis covers software and hardware implementations, discussing each method's challenges, benefits, and trade-offs. By examining the state-of-the-art in this field, this paper provides valuable insights and guidance for researchers and engineers working on time-critical applications in RISC-V-based embedded systems, aiding in selecting the most-suitable stack for their designs. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The Lorentz transformations transform the coordinates in a frame at rest and those in a frame moving with a constant velocity with respect to the rest frame. We analyze the Lorentz transformations using a world line diagram and simple algebra, obtaining some astonishing results. We use two examples to demonstrate that the Lorentz transformations contradict reality and are invalid. Employing the proper definition of simultaneity, we formulate the coordinate transformations between the two frames and obtain the Galileo transformations. Additionally, we suppose A, M, and B are points on the x-axis moving in the x direction and the distances AM = MB. Source S rests on the x-axis and emits signals when S and M coincide. The emitted signal reaches A earlier than it reaches B. In other words, A, which is approaching the signal source, receives the signal earlier than B, which is moving away from the signal source. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Test & Measurement Technology is the property of Publishing Center of North University of China and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps.

The Internet of Things (IoT) aims to revolutionize users' daily lives by enabling seamless data exchange among various ubiquitous devices over the Internet. However, achieving this broad objective can pose significant challenges for applications that require synchronized timing, such as ensuring the temporal sequencing of data or synchronized performance of activities. IoT networks typically comprise entities with varying resources, making it challenging to implement existing time synchronization methods like N.T.P. (Network Time Protocol) on resource-constrained devices. On the other hand, solutions that work for constrained systems may not be scalable across diverse IoT deployments. This survey paper delves into the clock synchronization issues in IoT installations where applications require a unified perception of time. The article describes clock synchronization solutions for various models and their associated performance and discusses several research challenges related to clock synchronization. Additionally, a review of time synchronization techniques is provided to aid IoT practitioners in selecting the most relevant aspects for deployment.

In this work, we have built an experimental setup to simulate the clock noise transmission between two spacecrafts, and further demonstrated the extraction of picometer level signal drowned by the large laser frequency noise and clock noise with the data post-processing method. Laser frequency noise is almost eliminated by using the idea of time-delay interferometry (TDI) to construct an equal arm interferometer. Clock asynchronism and clock jitter noise are significantly suppressed by laser sideband transmitting the clock noise with an electro-optic modulator (EOM). Experimental results show a reduction in laser frequency noise by approximately 105 and clock noise by 102, recovering a weak displacement signal with an average amplitude about 60 picometer and period 1 s. This work has achieved the principle verification of the noise reduction function of TDI technique to some extent, serving the data processing research of space-borne gravitational wave detection.

With the continual technical advancement, the requirements for the performance of the EtherCAT master station are raised in high-end applications. The EtherCAT master station configured with traditional software runs Windows or Linux operating system, completely depending on the real-time capability of the operating system regarding performance and stability, and suffering from jitter generally at the microsecond level, so it can hardly meet the requirements in high-end applications. In addition, the clock of the first slave station is used as the system clock for the traditional clock synchronization algorithm, imposing certain limitations. Therefore, this paper first elaborates the current status of the EtherCAT master station research, and then proposes an FPGA-based hardware EtherCAT master station scheme and a DC synchronization algorithm based on the FPGA master clock, followed by the description on the implementation method of the hardware EtherCAT master station; the final part contains the experimental verification on the proposed master station system with six general-purpose servo drives as the slave devices. Base on the verification results, with only 5 ns data frame jitter in the master station communication of the current design and with the clock synchronization algorithm described herein, SYNC0 interrupts are synchronized in real time among slaves, which can meet the requirements of various high-end application scenario; moreover this master station can be flexibly applied to different hardware platforms due to the portability of FPGA codes, which has a strong engineering guiding significance.

Clock synchronization is one of the popular research topics in Distributed Measurement and Control Systems (DMCSs). In most industrial fields, such as Smart Grid and Flight Test, the highest requirement for synchronization accuracy is 1 μs. IEEE 1588 Precision Time Protocol-2008 (PTPv2) can theoretically achieve sub-microsecond accuracy, but it relies on the assumption that the forward and backward delays of PTP packets are symmetrical. In practice, PTP packets will experience random queue delays in switches, making the above assumption challenging to satisfy and causing poor synchronization accuracy. Although using switches supporting the Transparent Clock (TC) can improve synchronization accuracy, these dedicated switches are generally expensive. This paper designs a PTP clock servo for compensating Queue-Induced Delay Asymmetry (QIDA), which can be implemented based on ordinary switches. Its main algorithm comprises a minimum window filter with drift compensation and a fuzzy proportional–integral (PI) controller. We construct a low-cost hardware platform (the cost of each node is within USD 10) to test the performance of the clock servo. In a 100 Mbps network with background (BG) traffic of less than 70 Mbps, the maximum absolute time error (max |TE|) does not exceed 0.35 μs, and the convergence time is about half a minute. The accuracy is improved hundreds of times compared with other existing clock servos.

In order to improve clock synchronization precision of the power distribution field network, a power distribution field network with high‐speed power line broadband carrier communication is designed, and a step‐by‐step precision clock synchronization strategy is developed based on modified timing‐sync protocol for sensor networks. In the strategy, the clock of the central node is calibrated in real‐time as the master clock of the field network by the communication master station through the long‐distance communication network, the time and frequency deviations of the clocks of each node in the network are accurately monitored using the broadcast mechanism and the network time base of the carrier communication, and the clock frequency is gradually amended by re‐calibrating the clock temperature compensation coefficient of the node so that the clock of the node is synchronized step‐by‐step within a clock synchronization cycle. The clock synchronization performances of the field network are tested in the laboratory and jobsite, and test results show that the clock synchronization accuracy of the field network is within ± 0.23 s/24 h, which is 28% higher than that of the power distribution field network based on narrowband power line carrier, and these phenomena of time gap or time repetition are avoided in the clock synchronization process. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

The importance of synchronization of spatially separated clocks in observing event coordinates cannot be overemphasized. We illustrate this with a real-world example. The results show the dependence of both length contraction and time dilation on the adopted synchronization convention. It is illustrated that a change in synchronization convention completely alters the appearance of the physical world. This is to be viewed in the context of the stated position in physics that synchronization of spatially separated clocks in any inertial frame depended on the adoption of a convention for its resolution. The preferred method of synchronization of spatially separated clocks is the standard convention recommended by the theory of relativity; however, it still remains a convention. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) aims to revolutionize users’ daily lives by enabling seamless data exchange among various ubiquitous devices over the Internet. However, achieving this broad objective can pose significant challenges for applications that require synchronized timing, such as ensuring the temporal sequencing of data or synchronized performance of activities. IoT networks typically comprise entities with varying resources, making it challenging to implement existing time synchronization methods like N.T.P. (Network Time Protocol) on resource-constrained devices. On the other hand, solutions that work for constrained systems may not be scalable across diverse IoT deployments. This survey paper delves into the clock synchronization issues in IoT installations where applications require a unified perception of time. The article describes clock synchronization solutions for various models and their associated performance and discusses several research challenges related to clock synchronization. Additionally, a review of time synchronization techniques is provided to aid IoT practitioners in selecting the most relevant aspects for deployment. [ABSTRACT FROM AUTHOR]

The performance of time-critical systems depends heavily on time synchronization accuracy. Therefore, it is crucial to have a synchronization method that can achieve high time synchronization accuracy. In this paper, we propose a new underlying transmission architecture and new synchronization messages. On the basis of these, aiming at the time error problem of the slave clock, we propose an enhanced time synchronization method based on new synchronization messages. Furthermore, we evaluate the performance of the enhanced time synchronization method on the OMNeT++ simulator. In addition, we compare the impact of different crystal oscillator accuracies and different crystal oscillator frequencies on time synchronization accuracy, respectively. Simulation results show that the time offset is at most ±1 clock period using the enhanced time synchronization method. We realize the purpose of timing the master clock and the slave clock by counting the period of the clock signal. Therefore, we needed to round down the time count to an integer. This is the reason why −1 and 1 appear at the same time. When the crystal oscillator frequency used is 80 MHz, the system can achieve a time synchronization accuracy of ±12.5 ns; that is, a nanosecond-level time synchronization accuracy can be achieved. With the reduction of the crystal oscillator accuracy of the slave clock, the synchronization accuracy of ±1 clock period can still be achieved. With the increase in the crystal oscillator frequency, the time synchronization accuracy that can be achieved also improves. The method proposed in this paper provides a new way of thinking and has certain guiding significance for improving the time synchronization accuracy of time-critical systems. [ABSTRACT FROM AUTHOR]

Aiming at the slow speed of two-dimensional accurate positioning of TOF in coal mine sites, a two-dimensional positioning method based on TOF combined with TDOA was proposed to meet the needs of rapid localization in coal mine sites. Before positioning, a master base station and three slave base stations are grouped to be responsible for two-dimensional positioning of an area. When the identification card is in the area, the distance between the four base stations and the identification card can be measured by only one DS-TWR ranging. At the same time, TWR can use time stamp to realize UWB wireless clock synchronization. Optional three base stations and identification card ranging distance can realize two-dimensional positioning. Through random combination, four sets of two-dimensional coordinate data can be obtained. Kalman filtering can obtain more accurate two-dimensional coordinate data. The TOF combined with TDOA two-dimensional precise positioning method has the advantages of fast positioning speed, high positioning accuracy, and simple positioning process.

Nowadays, there is an increasing demand for complex behavioral models on the market, as simulation has become the main verification approach used for both analog and digital functionalities. One of the most popular mixed-signal simulators nowadays is Simulation Program for Integrated Circuits Emphasis (SPICE). Over the last decade, the digital part in circuits has become predominant, but this poses big challenges when developing SPICE simulation models, as the circuits are synchronized upon internal or external clock signals, where the frequency accuracy is mandatory. The existing SPICE based simulators have built-in options to measure the signal frequency and duty cycle, but only after the simulation has completed, and in this way the frequency information can not be used during the simulation to synchronize the clock signals. There is a lot of research on frequency measurement techniques in the literature, but this topic has not been translated and covered in SPICE until now. Implementing the physical frequency measurement circuits proposed previously in the literature would increase the models’ complexity and the simulation time, without benefitting the final user. For this reason, in this article, a novel frequency measurement methodology for clock synchronization in SPICE based simulators is proposed, which aims to provide accurate measured frequency and duty cycle values for the digital clock signals with a fast simulation time. The performance evaluation of this methodology is done using OrCAD Capture, which is the most popular SPICE-based simulation environment.

In regions where global navigation satellite systems (GNSS) signals are unavailable, such as underground areas and tunnels, GNSS simulators can be deployed for transmitting simulated GNSS signals. Then, a GNSS receiver in the simulator coverage outputs the position based on the received GNSS signals (e.g., Global Positioning System (GPS) L1 signals in this study) transmitted by the corresponding simulator. This approach provides periodic position updates to GNSS users while deploying a small number of simulators without modifying the hardware and software of user receivers. However, the simulator clock should be synchronized to the GNSS satellite clock to generate almost identical signals to the live-sky GNSS signals, which is necessary for seamless indoor and outdoor positioning handover. The conventional clock synchronization method based on the wired connection between each simulator and an outdoor GNSS antenna causes practical difficulty and increases the cost of deploying the simulators. This study proposes a wireless clock synchronization method based on a private time server and time delay calibration. Additionally, we derived the constraints for determining the optimal simulator coverage and separation between adjacent simulators. The positioning performance of the proposed GPS simulator-based indoor positioning system was demonstrated in the underground testbed for a driving vehicle with a GPS receiver and a pedestrian with a smartphone. The average position errors were 3.7 m for the vehicle and 9.6 m for the pedestrian during the field tests with successful indoor and outdoor positioning handovers. Since those errors are within the coverage of each deployed simulator, it is confirmed that the proposed system with wireless clock synchronization can effectively provide periodic position updates to users where live-sky GNSS signals are unavailable.

There are two common approaches to design a time synchronization protocol as reference-based and consensus-based. The first approach is mainly employed in protocols operating in large-scale wireless sensor networks (WSNs) because of its fast convergence. However, reference-based time synchronization protocols are vulnerable to node-failure in real-world applications. Although consensus-based time synchronization protocols do not experience the aforementioned problem, they are not suitable for operation in large-scale WSNs owing to their slow convergence. In this study, we propose a hybrid time synchronization protocol (HTSP) to utilize the advantages of both approaches. In particular, HTSP exploits a temporary reference node to significantly reduce the convergence time and employs average-based consensus during normal operation to cope with node failures. It is notable that each node in HTSP can seamlessly switch between the reference and consensus modes during its operation. Moreover, HTSP is a fully distributed protocol as it does not rely on any leader-election mechanism. Our simulation results demonstrated that HTSP outperforms flooding, gradient, and virtual link-based time synchronization protocols considering various types of network topologies and scales.

The rapid development of multi-satellite formations requires inter-satellite radio frequency (RF) measurement to be both precise and scalable. The navigation estimation of multi-satellite formations using a unified time reference demands the simultaneous RF measurement of the inter-satellite range and time difference. However, high-precision inter-satellite RF ranging and time difference measurements are investigated separately in existing studies. Different from the conventional two-way ranging (TWR) method, which is limited by its reliance on a high-performance atomic clock and navigation ephemeris, asymmetric double-sided two-way ranging (ADS-TWR)-based inter-satellite measurement schemes can eliminate such reliance while ensuring measurement precision and scalability. However, ADS-TWR was originally proposed for ranging-only applications. In this study, by fully exploiting the time-division non-coherent measurement characteristic of ADS-TWR, a joint RF measurement method is proposed to obtain the inter-satellite range and time difference simultaneously. Moreover, a multi-satellite clock synchronization scheme is proposed based on the joint measurement method. The experimental results show that when inter-satellite ranges are hundreds of kilometers, the joint measurement system has a centimeter-level accuracy for ranging and a hundred-picosecond-level accuracy for time difference measurement, and the maximum clock synchronization error was only about 1 ns. [ABSTRACT FROM AUTHOR]

In view of the problem of clock Byzantine failure and node communication link loss failure in the non-master clock synchronization in the distributed real-time system, a fault-tolerant clock synchronization algorithm based on gray prediction is proposed in this study. The proposed algorithm is based on the LL model of the broadcast communication network, and uses the gray prediction method of GM（1,1） to analyze the correction deviation value of the previous round, so as to predict the correction deviation value of the node in the failure order, and then obtain the correction value through calculation. The experimental results show that the gray prediction algorithm proposed in this study can tolerate Byzantine faults, and at the same time, it can overcome the problems caused by the failure of node communication link loss, and improve the universality of the FTA algorithm. The data comparison analysis results show that the clock synchronization precision of this algorithm is improved by 24.3% when compared with Original algorithm. At the same time, the algorithm complexity has certain advantages when compared with other algorithms. [ABSTRACT FROM AUTHOR]

Copyright of Electric Power is the property of Electric Power Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Clock synchronization is one of the most fundamental and crucial network communication strategies. With the expansion of the Industrial Internet in numerous industrial applications, a new requirement for the precision, security, complexity, and other features of the clock synchronization mechanism has emerged in various industrial situations. This paper presents a study of standardized clock synchronization protocols and techniques for various types of networks, and a discussion of how these protocols and techniques might be classified. Following that is a description of how certain clock synchronization protocols and technologies, such as PROFINET, Time-Sensitive Networking (TSN), and other well-known industrial networking protocols, can be applied in a number of industrial situations. This study also investigates the possible future development of clock synchronization techniques and technologies. [ABSTRACT FROM AUTHOR]

Owing to its unique, concealment and easy customization by combining different wrist and hand gestures, high-density surface electromyogram (HD-sEMG) is recognized as a potential solution to the next generation biometric authentication, which usually adopts a wireless body sensor network (BSN) to acquire the multi-channel HD-sEMG biosignals from distributed electrode arrays. For more accurate and reliable classification, biometric authentication requires the distributed biosignals to be sampled simultaneously and be well aligned, which means that the sampling jitters among the arrays need to be tiny. To synchronize data sampling clocks of a cluster of BSN nodes for biometric authentication, this article modifies the packet-coupled oscillators protocol by using a dynamic controller (D-PkCOs). This protocol only involves one-way single packet exchange, which reduces the communication overhead significantly. For the purpose of maintaining precise sampling of these BSN nodes subject to drifting clock frequency and varying delays, the dynamic controller is designed via the $H_\infty$ robust method, and it is proved that all the BSN nodes’ sampling jitters are bounded. The experimental results demonstrate that the D-PkCOs protocol can keep the sampling jitters less than a microsecond in a 10-node IEEE 802.15.4 network. The application of D-PkCOs to the BSN shows that the HD-sEMG signal with a high signal-to-noise ratio is obtained, which leads to better gesture classification performance. [ABSTRACT FROM AUTHOR]

There are two common approaches to design a time synchronization protocol as reference-based and consensus-based. The first approach is mainly employed in protocols operating in large-scale wireless sensor networks (WSNs) because of its fast convergence. However, reference-based time synchronization protocols are vulnerable to node-failure in real-world applications. Although consensus-based time synchronization protocols do not experience the aforementioned problem, they are not suitable for operation in large-scale WSNs owing to their slow convergence. In this study, we propose a hybrid time synchronization protocol (HTSP) to utilize the advantages of both approaches. In particular, HTSP exploits a temporary reference node to significantly reduce the convergence time and employs average-based consensus during normal operation to cope with node failures. It is notable that each node in HTSP can seamlessly switch between the reference and consensus modes during its operation. Moreover, HTSP is a fully distributed protocol as it does not rely on any leader-election mechanism. Our simulation results demonstrated that HTSP outperforms flooding, gradient, and virtual link-based time synchronization protocols considering various types of network topologies and scales. [ABSTRACT FROM AUTHOR]

The concept of inertial frame of reference in classical physics and special theory of relativity is analyzed. It has been shown that this fundamental concept of physics is not clear enough. A definition of inertial frame of reference is proposed which expresses its key inherent property. The definition is operational and powerful. Many other properties of inertial frames follow from the definition, or it makes them plausible. In particular, the definition shows why physical laws obey space and time symmetries and the principle of relativity, it resolves the problem of clock synchronization and the role of light in it, as well as the problem of the geometry of inertial frames.

The information theoretically secure Kirchhoff-law-Johnson-noise (KLJN) key exchange scheme, similarly to quantum key distribution (QKD), is also potentially vulnerable against clock attacks, where Eve takes over the control of clock synchronization in the channel. This short note aims to introduce a time synchronization protocol scheme for Alice and Bob, which is resistant against arbitrary time delay attacks, both symmetric and asymmetric ones. We propose and explore various ways of clock synchronization for the KLJN system and propose an ultimate protocol that preserves time and hardware integrity under arbitrary attacks. [ABSTRACT FROM AUTHOR]

EtherCAT is one of the preferred real-time Ethernet technologies. However, EtherCAT is not applicable in high-end control fields due to real-time constraints. Clock synchronization and cycle time are the most representative limitations. In this paper, a novel Heterogeneous Parallel System Architecture (HPSA) with features of parallel computation and hard real-time is presented. An HPSA-based EtherCAT hard real-time master is developed to significantly improve clock synchronization and shorten cycle time. Traditional EtherCAT masters feature serial processing and run on a PC. This HPSA-based master consists of two parts: EtherCAT master stack (EMS) and EtherCAT operating system (EOS). EMS implements the parallel operation of EtherCAT to realize the shorter cycle time, and EOS brings a hard real-time environment to the HPSA-based master to improve clock synchronization. Furthermore, this HPSA-based master operates on a heterogeneous System-on-a-chip (SoC). EMS and EOS form a heterogeneous architecture inside this SoC to achieve low-latency process scheduling. Experimental results show that in our HPSA-based EtherCAT hard real-time master, the cycle time reaches the sub-50 μ s range, and the synchronization error reduces to several nanoseconds. Thus, this HPSA-based master has great application value in high-performance control systems. [ABSTRACT FROM AUTHOR]

Modern cars are characterized by a growing number of sensors, actuators, and advanced driver assistance systems that require a synchronized view of the time. These devices are typically interconnected by CAN, which is still the most important in-vehicle network. Precise clock synchronization over CAN is difficult due to the properties of the bus, and current approaches often use dedicated hardware or proprietary software solutions. A few years ago, however, the AUTomotive Open System ARchitecture (AUTOSAR) development alliance published a standardized synchronization method. In this article, we investigate what synchronization precision can be realistically achieved in a real-world automotive hardware and software environment. This involves pure software timestamping, standard CAN controllers without hardware modifications, and a typical automotive real-time operating system. We evaluate several approaches to reduce the synchronization jitter using filtering and optimizing the timestamping procedure. Experiments show that, ultimately, a precision better than 50 $\mu$ s can be achieved with a fully AUTOSAR-compliant software implementation. [ABSTRACT FROM AUTHOR]

In modern medicine, smart wireless connected devices are gaining an increasingly important role in aiding doctors’ job of monitoring patients. More and more complex systems, with a high density of sensors capable of monitoring many biological signals, are arising. Merging the data offers a great opportunity for increasing the reliability of diagnosis. However, a huge problem is constituted by synchronization. Multi-board wireless-connected monitoring systems are a typical example of distributed systems and synchronization has always been a challenging issue. In this paper, we present a distributed full synchronized system for monitoring patients’ health capable of heartbeat rate, oxygen saturation, gait and posture analysis, and muscle activity measurements. The time synchronization is guaranteed thanks to the Fractional Low-power Synchronization Algorithm (FLSA). [ABSTRACT FROM AUTHOR]

The clock synchronization is a key technology for the reliability of wireless sensor networks (WSN). To reduce the communication burden and address the challenge of clock synchronization for high-precise clock systems in WSN with switching topologies, this paper proposes an event-triggered synchronization strategy for high-precise clock systems. Firstly, based on the concept of offset and skew, the model of whole clock systems is investigated and an event-triggered strategy is proposed for high-precise clock systems with switching topologies. Then, a synchronization strategy for clock systems is presented to achieve clock synchronization with the convergence of clock offset and clock skew. The sufficient condition for the synchronization of high-precise clock systems with switching topologies is obtained. Afterwards, the optimal event-triggered weighting matrices and controller gains are calculated by converting the clock synchronization problem as a solvable optimization problem. Finally, the performance of the proposed clock synchronization method is evaluated by simulations., Competing Interests: The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper., (© 2024 The Author(s).)

With the rapid development of information technology, high-speed digital optical signal transmission technology has become the core of modern communication networks. However, the increase in transmission rates brings challenges such as noise, distortion, and interference, which affect the accuracy of clock recovery. To address these issues, this study proposes a clock recovery algorithm based on the eye diagram opening area to improve the accuracy and efficiency of high-speed digital optical signal jitter measurement. The proposed method extracts clock information from the signal using the opening area and curvature characteristics of the eye diagram for jitter measurement. Experimental results demonstrate that the clock recovery algorithm based on the eye diagram opening area can stably reconstruct the signal eye diagram and obtain jitter parameters under different optical power conditions. At optical powers of -7.2 dBm, -12.2 dBm, and -17.2 dBm, the Q-factors were 8.8, 7.6, and 4.3, respectively, and the RMS jitter values were 12.2 ps, 13.4 ps, and 21.2 ps, respectively. At optical powers of -2.3 dBm, 0.1 dBm, 2.4 dBm, 4.6 dBm, and 6.0 dBm, the Q-factors were 9.1, 9.3, 9.5, 9.7, and 10.0, respectively, and the average jitter values were 8.9 ps, 8.5 ps, 8.0 ps, 7.5 ps, and 7.0 ps. These results indicate that the proposed algorithm performs excellently under low optical power conditions and maintains high recovery accuracy even when jitter increases at higher optical powers. The clock recovery algorithm based on the eye diagram opening area significantly improves the accuracy and stability of high-speed digital optical signal jitter measurement, enriches the theoretical research of clock recovery algorithms, and shows significant advantages in improving signal transmission quality, reducing bit error rate, and enhancing communication link reliability. The research outcomes provide key technical support for the optimization of modern high-speed optical communication systems., Competing Interests: The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper., (© 2024 The Author.)

Clock synchronization provides fundamental timing reference for various services in the Internet of Things. Unlike centralized synchronization algorithm, which relies heavily on the synchronization routing and brings about error accumulation consequently, the distributed synchronization algorithm achieves clock synchronization through time message exchange and calculation among adjacent nodes, hence the error accumulation can be greatly eliminated. However, the convergence speed of existing distributed synchronization algorithms is generally slow, and network topology information is seldom utilized to improve the convergence speed, which may cause additional energy consumption, especially in resource-constrained scenarios. To improve the convergence speed of distributed clock synchronization, a consensus tracking-based clock synchronization (CTCS) algorithm is proposed in this paper. By analyzing the synchronization process in the state space framework, the convergence acceleration term is designed to optimize the eigenvalue distribution of synchronization error matrix, hence the convergence speed can be greatly improved. To be suitable for clock synchronization in the dynamic network, a reference clock input term is designed in the clock update formula, which eliminates the oscillation of synchronized clocks triggered by synchronization of newly joined nodes. To prove the convergence of CTCS, an in-depth analysis of the algorithm is conducted. Both simulation and experimental results validate the effectiveness of CTCS in comparison with other solutions. [ABSTRACT FROM AUTHOR]

Time triggered communication provides fault tolerance and determinism in a distributed dependable real time systems. These systems crucially depend on fault tolerant clock synchronization. The article presents simulation of fault tolerant averaging algorithm for clock synchronization and it's modification for improved convergence. We present the simulation results of synchronization algorithm to verify fault tolerance and convergence to a single time base. By modification, we show how a two node system can also be synchronized eliminating the criteria of minimum three nodes. This article also reports a custom time triggered protocol named as deterministic fault tolerant communication protocol particularly suitable for mission critical applications or safety-critical control applications such as in automotive “by-wire” and aerospace systems. The article also presents a different approach for membership service which is based on majority voting and can be used in systems based on time triggered architecture. [ABSTRACT FROM AUTHOR]

In wireless application, mobile low duty cycle wireless sensor network (MLDC‐WSN) gained more attention among the researchers, because it includes advantages like growing node life, saving node power, and network reliability. However, the sleeping features and mobility of MLDC‐WSN results in topology change that restricts the speed of neighbor node discovery. To highlight this concern, a novel routing protocol named as improved Bayesian clock synchronization‐gossip routing protocol is proposed for an effective neighbor node discovery in MLDC‐WSN. The proposed routing protocol reduces end‐to‐end delay, and clock drifts problems. Also, the proposed routing protocol improves the clock synchronization and captures the neighbor discovery nodes by identifying the next neighbor set in the next moment, due to the prediction of the distance and movement speed of neighbors. Simulation and analytical results showed that the proposed routing protocol superiorly decreases the end‐to‐end delay and energy consumption compared to the existing algorithms. [ABSTRACT FROM AUTHOR]