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Analog computing is attractive compared to digital computing due to its potential for achieving higher computational density and higher energy efficiency. However, unlike digital circuits, conventional analog computing circuits cannot be easily mapped across different process nodes due to differences in transistor biasing regimes, temperature variations and limited dynamic range. In this work, we generalize the previously reported margin-propagation-based analog computing framework for designing novel \textit{shape-based analog computing} (S-AC) circuits that can be easily cross-mapped across different process nodes. Similar to digital designs S-AC designs can also be scaled for precision, speed, and power. As a proof-of-concept, we show several examples of S-AC circuits implementing mathematical functions that are commonly used in machine learning (ML) architectures. Using circuit simulations we demonstrate that the circuit input/output characteristics remain robust when mapped from a planar CMOS 180nm process to a FinFET 7nm process. Also, using benchmark datasets we demonstrate that the classification accuracy of a S-AC based neural network remains robust when mapped across the two processes and to changes in temperature., Comment: 14 Pages, 15 Figures, 5 Tables. This work has been accepted in IEEE for publication. Copyright may be transferred without notice, after which this version may no longer be accessible

The development of a cost-efficient device to rapidly detect pandemic viruses is paramount. Hence, an innovative and scalable synthesis of metal nanoparticles followed by its usage for rapid detection of severe acute respiratory syndrome coronavirus-2 (SARS-CoV-2) has been reported in this work. The simple synthesis of metal nanoparticles utilizing tin as a solid-state reusable reducing agent is used for the SARS-CoV-2 ribonucleic acid (RNA) detection. Moreover, the solid-state reduction process occurs faster and leads to the enhanced formation of silver and gold nanoparticles (AuNPs) with voltage. By adding tin as a solid-state reducing agent with the precursor, the nanoparticles are formed within 30 s. This synthesis method can be easily scaled up for a commercially viable process to obtain different-sized metal nanoparticles. This is the first disclosure of the usage of tin as a reusable solid-state reducing agent for metal nanoparticle synthesis. An electronic device, consisting of AuNPs functionalized with a deoxyribonucleic acid (DNA)-based aptamer, can detect SARS-CoV-2 RNA in less than 5 min. With an increase in SARS-CoV-2 variants, such as Delta and Omicron, the detection device could be used for identifying the nucleic acids of the COVID-19 variants by modifying the aptamer sequence. The reported work overcomes the drawbacks of complex instrumentation, trained labor, and increased turnaround time.

Bias-scalable analog computing is attractive for implementing machine learning (ML) processors with distinct power-performance specifications. For instance, ML implementations for server workloads are focused on higher computational throughput for faster training, whereas ML implementations for edge devices are focused on energy-efficient inference. In this paper, we demonstrate the implementation of bias-scalable approximate analog computing circuits using the generalization of the margin-propagation principle called shape-based analog computing (S-AC). The resulting S-AC core integrates several near-memory compute elements, which include: (a) non-linear activation functions; (b) inner-product compute circuits; and (c) a mixed-signal compressive memory, all of which can be scaled for performance or power while preserving its functionality. Using measured results from prototypes fabricated in a 180nm CMOS process, we demonstrate that the performance of computing modules remains robust to transistor biasing and variations in temperature. In this paper, we also demonstrate the effect of bias-scalability and computational accuracy on a simple ML regression task., 11 pages, 11 figures, 2 Tables