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In digital integrated circuits with multiple power domains, level shifters (LSs) are essential circuit elements that can transform the voltage region from low to high. However, high-frequency gate drivers can generate hundreds of voltages per nanosecond noise (high dV/dt noise). Such high dV/dt noise can cause malfunction of a conventional pulse-triggered cross-coupled LS (CCLS) that is used to control the high-side nMOS switch. In this article, a novel LS with noise immunity is proposed and investigated. Compared with the conventional resistor load LS, the proposed circuit adopts nMOS-R cross-coupled (NRCC) LS, and realizes the selective filtering ability by exploiting the path that filters out the noise introduced by the dV/dt. The high-voltage gate drive integrated circuit (HVIC) is implemented using a 600 V silicon-on-insulator (SOI) BCD process. Analyses and experiments show that the proposed design can help the HVIC maintain a high common-mode transient immunity (CMTI) of up to 137 V/ns while allowing a negative VS swing down to -9.4 V under a 15 V supply voltage. Compared with the traditional HVIC with resistance load LS, the proposed novel HVIC with the NRCC LS improves the noise immunity of dV/dt by 182%.

This article investigates the degradation mechanism in dV/dt noise immunity robustness of traditional resistive load level shifters (LSs) under total-ionizing-dose (TID) irradiation and proposes a novel radiation-hardened nMOS-R cross-coupled (NRCC) LS with dV/dt noise immunity. When TID irradiation induces threshold voltage drift and increases the off-state leakage current in power devices, the proposed circuit employs a differential and complementary structure to counteract the degradation of electrical performance in both branches caused by the TID irradiation, thereby achieving improved radiation-hardening performance. Measurement results demonstrate that the proposed high-voltage gate drive integrated circuit (HVIC) with the novel LS level exhibits 130-V/ns noise immunity at the irradiation dose of 100 krad(Si). A normalization method is used to process measurement results for visual comparison. The degradation of dV/dt noise immunity capability of the proposed LS is improved by 26.8%, 72.4%, and 94.9% compared with the traditional LS at the irradiation dose of 30, 50, and 100 krad(Si). The HVIC is implemented using a 600-V silicon-on-insulator (SOI) BCD process.

The total-ionizing-dose (TID) effect has different influences on bipolar junction transistors (BJTs), resistors, and MOSFETs, which leads to significant drifts in the overtemperature threshold in the traditional overtemperature protection circuit (OTPC). An OTPC with a dynamic comparison technique is proposed to improve the radiation-hardened capability. The proposed radiation-hardened OTPC employs two identical sensors to monitor the temperature and convert it into voltage for comparison to determine if overtemperature occurs. The voltage drifts caused by TID effects on two sensors vary dynamically and offset each other, so the overtemperature threshold will not drift theoretically. The normalization method is used to process measurement results to get a visual comparison. The measurement results show that the threshold drift of the proposed OTPC is 5.0% lower than that of traditional OTPC at 30 krad(Si), 7.1% lower at 50 krad(Si), and 10.3% lower at 100 krad(Si). Therefore, the proposed OTPC reduces the threshold voltage drifts effectively and has a good radiation-hardened effect.