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With the continuous scaling of CMOS technology, single-event multi-node upsets (MNU) induced by charge sharing has continued to occur in latches when hit by high-energy particles. This paper presents a quadruple-node upset (QNU) tolerant latch design (referred to as P-DICE latch) to achieve both high reliability and low area overhead. The P-DICE latch takes advantage of the error-blocking properties of Cross-Coupled Element and C Element to tolerate QNU, and achieves 100% self-recovery of SNU and DNU. Compared with previous eight MNU hardened latches, the P-DICE latch has the lowest overhead in terms of area, area-power-delay product (APDP), and area-power-delay soft error rate ratio product (APDSP), and has the highest critical charge. Moreover, the proposed P-DICE latch can tolerate QNU caused by high-energy particles to ensure the reliability of the circuit. Compared with eight MNU hardened latches, the proposed P-DICE latch achieves 24.58% reduction in area, 33.05% reduction in power, 17.19% reduction in delay, 48.29% reduction in area-power-delay product, 61.60% reduction in APDSP, and 142.82% improvement in critical charge on average. [ABSTRACT FROM AUTHOR]

This paper presents a novel radiation hardened latch (namely DCTELC) that can completely tolerate single-node upsets and double-node upsets (DNUs) for high-performance applications. The latch mainly consists of a clock-gating based dual-interlocked-cell (DICE), a 2-input C-element, and a clock-gating based 2-input C-element. The latch introduces isolated nodes to tolerate DNUs and the isolated nodes have no time to float for high-performance applications. Simulation results demonstrate the complete DNU tolerance for the latch and an 86% power-area-delay product (PADP) saving on average compared with state-of-the-art DNU-tolerant latches. Moreover, compared with the existing latches of the same type, the power dissipation, silicon area, transmission delay, and PADP of the proposed latch are the smallest. • A double-node-upset completely tolerant CMOS latch design is proposed. • The latch has extremely low cost compared with the same type latches. • The latch is suitable for high-performance applications due to low delay. [ABSTRACT FROM AUTHOR]

With the continuous scaling of CMOS feature sizes, single event triple-node-upset (TNU) induced by charge sharing has become a serious reliability issue. This paper presents a low-cost triple-node-upset self-recovery latch (LC-TSL) which is composed of N-elements, P-elements and C-elements. The LC-TSL utilizes a two-dimensional feedback array composed of four rows and four columns to achieve triple-node-upset recovery. It utilizes high-speed transmission path to achieve high performance and clock-gating to reduce power consumption. The extensive simulation results show that the LC-TSL achieves high speed, low power consumption and 100% TNU recovery. Compared with the average of previous eight hardened latches, the LC-TSL reduces the delay by 78.59% and reduces the power-delay-product by 79.69%, while only increases 15.15% area overhead and 15.38% power consumption overhead. Compared with TNU self-recoverable latches, the LC-TSL is the best in terms of area, delay, and PDP. The LC-TSL achieves TNU-recovery ability and low cost overhead, and it is insensitive to voltage and temperature variations. [ABSTRACT FROM AUTHOR]

With the continuous scaling of IC technology, latches becomes more vulnerable to double-node-upset (DNU) and triple-node-upset (TNU). The node separated (NS) method applied for DNU hardening has not been used for TNU hardening to effectively reduce the probability of TNU occurrence, resulting in excessive power consumption, delay and area overhead of TNU hardening. This paper proposes a low-overhead TNU self-recoverable latch, named Node Separated Triple-node-upset Self-recoverable Latch (NS-TSL). NS-TSL includes four N-type stacked structures, four P-type stacked structures, a clock gating based inverter, and a high-speed transmission path. Based on a physical flip mechanism that makes sensitive nodes flip in one direction and multiple feedback mechanism, NS-TSL can realize TNU self-recovery. Simulation results demonstrate that compared with the other six TNU hardened latches, NS-TSL reduces the delay by 62.24%, the power consumption by 59.96%, the power delay product by 84.04%, and the area by 27.97% on average. Moreover, NS-TSL is insusceptible to temperature and voltage variations. [ABSTRACT FROM AUTHOR]