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Scientists without specific software programming skills are increasingly required to express their problems in terms of software to exploit the computational power of heterogeneous parallel hardware. Producing software for this hardware is very cumbersome for the experienced programmer; for the novice, it is just impracticable. We aim to grant scientists across disciplines access to heterogeneous hardware via a model-driven holistic approach. Via proper software modelling, we suppress the need to write resource-specific software functions and complex offloading and communication code; we will do this by devising a comprehensive modelling language that implicitly underpins multiple execution semantics (sequential, data-/task-parallel). Current code generators neglect model semantics while compilers expect in input too detailed software descriptions; we will devise an innovative semantics-aware model compiler with automatic parallelization. Overall, we aim at giving researchers and practitioners better tools to focus more on the problem to solve than learning how to master complex techniques and languages to describe it in terms of software. Moreover, the learning curve and technological hindrances for beginners approaching hybrid software will be pushed down dramatically., Conference paper; Export Date: 17 April 2024; Cited By: 0; Correspondence Address: F. Ciccozzi; Mälardalen University, School of Innovation, Design, and Engineering, Västerås, Sweden; email: federico.ciccozzi@mdu.se; Conference name: 2024 International Conference on Artificial Intelligence, Computer, Data Sciences, and Applications, ACDSA 2024; Conference date: 1 February 2024 through 2 February 2024; Conference code: 198277

Heterogeneous systems, consisting of CPUs and GPUs, offer the capability to address the demands of compute- and data-intensive applications. However, programming such systems is challenging, requiring knowledge of various parallel programming frameworks. This paper introduces COMPAR, a component-based parallel programming framework that enables the exposure and selection of multiple implementation variants of components at runtime. The framework leverages compiler directive-based language extensions to annotate the source code and generate the necessary glue code for the StarPU runtime system. COMPAR provides a unified view of implementation variants and allows for intelligent selection based on runtime context. Our evaluation demonstrates the effectiveness of COMPAR through benchmark applications. The proposed approach simplifies heterogeneous parallel programming and promotes code reuse while achieving optimal performance. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024.

The utilization of performance monitoring probes is a valuable tool for programmers to gather performance data. However, the manual insertion of these probes can result in an increase in code size, code obfuscation, and an added burden of learning different APIs associated with performance monitoring tools. To mitigate these issues, EDPM, an embedded domain-specific language, was developed to provide a higher level of abstraction for annotating regions of code that require instrumentation in C and C++ programs. This paper presents the design and implementation of EDPM and compares it to the well-known tool PAPI, in terms of required lines of code, flexibility in configuring regions, and performance overhead. The results of this study demonstrate that EDPM is a low-resolution profiling tool that offers a reduction in required lines of code and enables programmers to express various configurations of regions. Furthermore, the design of EDPM is such that its pragmas are ignored by the standard compiler, allowing for seamless integration into existing software processes without disrupting build systems or increasing the size of the executable. Additionally, the design of the EDPM pre-compiler allows for the extension of available performance counters while maintaining a high level of abstraction for programmers. Therefore, EDPM offers a promising solution to simplify and optimize performance monitoring in C and C++ programs. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024.

Understanding the behavior of source code written in an unfamiliar programming language is difficult. One way to aid understanding of difficult code is to add corresponding pseudo-code, which describes in detail the workings of the code in a natural language such as English. In spite of its usefulness, most source code does not have corresponding pseudo-code because it is tedious to create. This paper demonstrates a tool Pseudogen that makes it possible to automatically generate pseudo-code from source code using statistical machine translation (SMT). Pseudogen currently supports generation of English or Japanese pseudo-code from Python source code, and the SMT framework makes it easy for users to create new generators for their preferred source code/pseudo-code pairs., ASE 2015 : 2015 30th IEEE/ACM International Conference on Automated Software Engineering, 9-13 Nov. 2015, Lincoln, NE, USA

Probabilistic programming languages (PPLs) allow users to encode arbitrary inference problems, and PPL implementations provide general-purpose automatic inference for these problems. However, constructing inference implementations that are efficient enough is challenging for many real-world problems. Often, this is due to PPLs not fully exploiting available parallelization and optimization opportunities. For example, handling probabilistic checkpoints in PPLs through continuation-passing style transformations or non-preemptive multitasking—as is done in many popular PPLs—often disallows compilation to low-level languages required for high-performance platforms such as GPUs. To solve the checkpoint problem, we introduce the concept of PPL control-flow graphs (PCFGs)—a simple and efficient approach to checkpoints in low-level languages. We use this approach to implement RootPPL: a low-level PPL built on CUDA and C++ with OpenMP, providing highly efficient and massively parallel SMC inference. We also introduce a general method of compiling universal high-level PPLs to PCFGs and illustrate its application when compiling Miking CorePPL—a high-level universal PPL—to RootPPL. The approach is the first to compile a universal PPL to GPUs with SMC inference. We evaluate RootPPL and the CorePPL compiler through a set of real-world experiments in the domains of phylogenetics and epidemiology, demonstrating up to 6 × speedups over state-of-the-art PPLs implementing SMC inference.

The cost of moving data between compute elements and storage elements plays a signiicant role in shaping the overall performance of applications.We present a compiler-driven approach to reducing data movement costs. Our approach, referred to as Computing with Near Data (CND), is built upon a concept called 'recomputation', in which a costly data access is replaced by a few less costly data accesses plus some extra computation, if the cumulative cost of the latter is less than that of the costly data access. Experimental result reveals that i) the average recomputability across our benchmarks is 51.1%, ii) our compiler-driven strategy is able to exploit 79.3% of the recomputation opportunities presented by our workloads, and iii) our enhancements increase the value of the recomputability metric signiicantly. © 2019 Copyright is held by the owner/author(s)., We thank Evgenia Smirni for shepherding our paper. We also thank the anonymous reviewers for their constructive feedback. Myoungsoo Jung is in part supported by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, IITP-2018-2017-0-01015, NRF 2015M3C4A7065645, Yonsei Future Research Grant (2017-22-0105) and Samsung grant (2018). This research is supported in part by NSF grants #1526750, #1763681, #1439057, #1439021, #1629129, #1409095, #1626251, #1629915, and a grant from Intel., 2017-22-0105; National Science Foundation, NSF: 1409095, 1439021, 1439057, 1526750, 1626251, 1629129, 1629915, 1763681; U.S. Department of Energy, USDOE: 2015M3C4A7065645, DEAC02-05CH11231; Intel Corporation; Samsung; National Research Foundation of Korea, NRF: 2016R1C1B2015312