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The series‐type direct current (DC) hybrid circuit breaker (S‐HCB) concept was previously reported to offer better performance than solid‐state circuit breakers (SSCB) and hybrid circuit breakers (HCB). S‐HCB offers low conduction power loss like an HCB and μs$\umu \text{s}$‐scale interruption time, which is even faster than an SSCB. It uses a pulse transformer to isolate the lower‐voltage high‐inductance power electronic circuit from the high‐voltage, low‐inductance main power loop. This paper provides analysis of the impact of the S‐HCB circuit components on the overall system performance and a scalable S‐HCB design guide for different DC system voltage and current ratings. In addition, system energy flow analysis is performed in the time domain to provide an understanding of how energy is delivered, dissipated, and released throughout the entire fault interruption process. The S‐HCB prototype was experimentally tested at 3 kV/30 A and 6 kV/150A with the results showing the interruption of the low fault current of 30 A and the high fault current of 150 A within 8 μs$\umu \text{s}$ and maintaining the fault current at a near zero value for 300μs$\nobreakspace \umu \text{s}$ to enable an arcless opening of a series mechanical switch. The key design challenges of S‐HCB at high voltage and high current ratings were discussed and possible solutions to mitigate those challenges were introduced. [ABSTRACT FROM AUTHOR]

The high‐voltage direct current (HVDC) power transmission short‐circuit fault protection is a big challenge, and it is the main obstacle to promote the HVDC multi‐terminal networks. A natural commutation current topology (NCCT) of hybrid HVDC circuit breaker (DCCB) integrated with limiting fault current is proposed in this paper, which shares several obvious merits, such as lower peak fault current, shorter fault isolation time and low turn‐off loss. The main contributions in this paper are made as follows. (1). A second‐order RLC circuit in novel NCCT circuit breaker is utilized as the current limiting circuit to dramatically reduce the fault current rising slope and its peak value. (2) A asynchronous NCCT circuit breaker has been investigated to broaden the proposed NCCT circuit breaker's optimal working area. (3) By taking China Zhangbei 500 kV four‐terminal DC grid as an example, an optimization design technique of the asynchronous NCCT‐DCCB is developed to demonstrate the process of the theoretical analysis and parameter design. The correctness of the proposed NCCT‐DCCB and the feasibility of the optimization design technique are confirmed by EMT simulation on PSCAD/EMTDC and hardware‐in‐loop experiment on PLECS‐RtBox. [ABSTRACT FROM AUTHOR]

Multi‐port hybrid DC circuit breakers (MP‐HCBs) are rapidly developing due to their obvious advantages in economy compared to traditional two‐port hybrid circuit breakers (HCBs). However, most of the existing MP‐HCB topologies do not have the current‐limiting capability, and a large number of insulated‐gate bipolar transistors (IGBTs) are still needed in their main breakers. In response to the problems, a multi‐port current‐limiting hybrid DC circuit breaker (MP‐CLHCB) based on thyristors is proposed in this paper. MP‐CLHCB uses low‐cost thyristors instead of IGBTs, and suppresses the rise of fault current through current‐limiting branch. In an attempt to prevent the MP‐CLHCB from reclosing in a permanent fault and causing damage to the DC grid again, an adaptive reclosing scheme is also proposed. In this paper, the topology, operation stages, theoretical derivation, and parameter design of the MP‐CLHCB are provided. Finally, the performance of the MP‐CLHCB is verified and compared through simulations in PSCAD/EMTDC. © 2021 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]