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Hybrid DC circuit breakers (HDCCBs) have excellent performance in terms of breaking speed and low losses and have become the mainstream technology for dc fault isolation in dc grids. However, because of the breaking limitation of the solid-state branch in HdcCBs, the existing HdcCBs are still weak in breaking high current. Although the breaking ability can be improved by series and parallel devices, the cost will increase rapidly, and it is very difficult to share current by paralleling a single type of device. This article proposes a novel HdcCB topology that combines two types of power electronic devices in solid-state branches to meet the requirement of a large breaking capacity in dc grids. The structure and breaking principles of this novel topology, which aims to break high current, are introduced. The design methods of the key parameters are presented. Then, the current breaking ability of the novel topology is verified by developing a prototype completing a 10 kV/60 kA breaking test in 3 ms. Finally, this novel topology is compared with other dc circuit breakers at the same breaking level, which shows that this novel topology has obvious advantages in cost and volume with fewer devices. [ABSTRACT FROM AUTHOR]

The multiterminal dc (MTDC) grid plays an important role in large-scale power transmission and renewable energy integration owing to its excellent performance. However, there are still some problems existing in the MTDC grid, such as difficult fault current interruption and current flow control, which impedes its development. Currently, the mentioned two problems can be separately solved by hybrid dc circuit breaker (HCB) and current flow controller (CFC). However, when configured separately, they are expensive and have large footprints. Therefore, this article proposes a multiport hybrid dc circuit breaker (MHCB) with current flow control capability. The HCBs near the same dc bus are first integrated into a single MHCB and then novel CFCs are embedded into the MHCB to replace the load commutation switches. Compared with the existing MHCBs, the proposed topology shows advantages in the aspects of implementation cost, power loss, and operation speed. The operation principle is analyzed and the basis for parameter design is given in detail. The effectiveness of the proposed topology is verified by extensive simulations and experiments. Besides, the proposed MHCB is compared with the existing solutions. [ABSTRACT FROM AUTHOR]

Superconductor–semiconductor hybrid circuits can combine the benefits of the high-speed and low-power operation of single-flux quantum circuits and high integration densities of CMOS technology such as memory. The Suzuki stack, a type of Josephson latching driver/amplifier, is a widely used interface circuit in Josephson–CMOS hybrid memories. Due to the limited cooling power at cryogenic temperatures, the power dissipation is becoming an important concern, especially in large-scale systems. An optimization technique to significantly reduce the power dissipation of Suzuki stack circuits is proposed in this article. The proposed design can reduce the power dissipation by 30–70% while causing a voltage drop of 2–9% in the output voltage depending on the circuit parameter configuration. The tradeoffs between the power dissipation and output voltage characteristics are discussed. The proposed design can operate correctly within at least $\pm$ 20% of process parameter variations as demonstrated with extensive simulations. [ABSTRACT FROM AUTHOR]

Piezoelectrically actuated fast mechanical switches provide a low-loss conduction path in hybrid circuit breakers for protecting medium-voltage direct-current systems. As the desired actuation speed approaches the driving limit of a piezoelectric actuator, excessive vibration starts to dominate its underdamped travel curves, resulting in insulation failures and delayed switching in the fast mechanical switch. To improve the underdamped travel curves into critically damped travel curves, several switching motion control schemes with active damping filters are proposed in this paper. The switching motion controllers are based on an electromechanical model of a fast mechanical switch with experimentally identified parameters. According to hardware implementation tests, the proposed closed-loop control schemes optimized the switch travel curves with a 56% reduction in the undershoot and a 75% reduction in the settling time. Equipped with the critically damped travel curves, the piezoelectrically actuated fast mechanical switch is better suited for sequential submodule operations to reduce the interruption time, the peak current and the fault energy to be absorbed in hybrid circuit breakers. [ABSTRACT FROM AUTHOR]

A high-efficiency ${D}$ -band monolithically integrated GaN frequency doubler based on a pair of antiseries four-anode planar GaN Schottky barrier diodes (SBDs) has been successfully fabricated. Unlike the traditional hybrid integrated circuit technology, the monolithic integrated circuit technology has been used in the design and fabrication of GaN SBD-based frequency doubler circuits to achieve good alignment and low conversion losses. At room temperature, the experiments show that the peak conversion efficiency reaches 17.0% at 115.6 GHz under a continuous wave (CW) driving which is a critical requirement for many practical applications. The efficiency of 17.0% is the highest efficiency of GaN SBD-based multipliers at present under CW driving mode. This monolithically integrated doubler also exhibits a broadband high efficiency characteristic of more than 4.7% (−5.58 dB from 17%) across a 10% band from 109 to 121 GHz. In addition, high CW power handling capability of the proposed frequency doubler is verified. The experiments show that the frequency doubler can endure a maximum CW input power of 0.5 W. [ABSTRACT FROM AUTHOR]

The dc circuit breaker plays an important protection role in the dc distribution systems. Hybrid dc circuit breaker (HCB) offers low conduction losses and reasonably fast response times. In this article, a high power density, modular, and scalable power electronic interrupter (PEI) design is introduced for medium-voltage (MV) HCB platforms. Following this concept, the single low-voltage module is first investigated in terms of the high pulse current ratio and the voltage clamping circuit. After the comparison and test among different devices, a compact module with 1.7-kV discrete IGBTs are selected as main switches. While the voltage clamping circuit is carefully designed to guarantee no tail current bump and sufficient turn-off voltage margin. Next the whole system with series modules is optimized on the aspects of the turn-off strategy, power supply structure, and layout of modules. An improved staged turn-off scheme is proposed, which can not only reduce the peak current and total metal oxide varistor (MOV) energy, but also help balance the MOV energy distribution. A 12-kV and 1-kV breaking capable PEI was demonstrated based on the proposed PEI design, achieving a peak power density of 7.4 kW/cm3, much higher than the IGBT module-based solution. The breaking capability and effectiveness of the modular PEI is demonstrated in a 6-kV MVDC HCB device. [ABSTRACT FROM AUTHOR]

High voltage direct current (HVdc) power transmission systems do not encounter any natural zero crossing unlike the ac systems, and hence, the dc circuit breakers employed should be fast-acting and reliable to ensure safe operation. Circuit breakers (CBs) that have fast response time with lower energy loss dissipation are required for subsea HVdc transmission systems. This article investigates the performance of various CB topologies, including ultrafast coupled inductor hybrid CB (CIHCB) topology without and with the integration of resistive-type superconducting fault current limiter (R-SFCL) for a 100-kV, 100-MW HVdc transmission systems. It is found that the addition of R-SFCL with 1.7-ms response time decreases the peak current through the breaker and, hence, the power dissipated in the CB during short-circuit fault conditions. Thus, the rating of CB can be significantly decreased with the proposed topology. Furthermore, a comparison of power loss in CIHCB with the existing topologies, such as mechanical CB, resonant CB, and HVdc-hybrid CB, are also presented in this article. [ABSTRACT FROM AUTHOR]

DC circuit breaker is the key equipment to deal with the interruption of short-circuit current. Compared with the mechanical switch, the solid circuit breaker and the hybrid circuit breaker using the semiconductor device to interrupt the short-circuit current exhibit superiorities in response duration and arc-less characteristics. Massive power devices controlled by corresponding gate drivers which make the semiconductors-based dc circuit breaker bulky and costly are required to withstand the high dc-bus voltage. In this article, the master−slave concept based modular circuit breaker is proposed to simplify the gate driver topology. Only one single gate driver is required to control highly compact modular submodules consisting of power devices, passive components, and diodes. Moreover, the proposed topology can be easily implemented with high flexibility and low cost. Specifically, the gate control function and voltage equalization for series-connected devices can be realized reliably. The master−slave concept and operation principle of the proposed topology are elaborated and the effectiveness has been demonstrated by both simulation and experimental test. [ABSTRACT FROM AUTHOR]

High-voltage direct current (HVDC) circuit breaker development and deployment strongly depend on the testing process, which ensures that the HVDC circuit breakers will satisfy design requirements. This article presents an HVDC circuit breaker test bench circuit configuration that can provide controllable large output currents to simulate different fault conditions for the current breaking test and high output voltage for the dielectric withstand test. The current breaking test circuit is based on multiple cascaded power converters connected in parallel to provide the necessary output current capability. Each cascaded power converter is composed of multiple cells that are operated by a phase-shifted pulsewidth-modulated signal for greater controllability and higher quality of the output waveform. The dielectric withstand test circuit is a simple high-voltage source with a low power rating that can also be used to charge the test bench and the internal circuitry of the circuit breaker that is to be tested. The proposed test bench ensures that fault conditions can be replicated accurately and offers greater flexibility by being able to test mechanical, semiconductor-based, or hybrid HVDC circuit breakers with different current and voltage ratings on the same hardware without any changes. The idea and the operating principle of the proposed test bench are verified experimentally on a downscaled system that consists of three cascaded power converters connected in parallel with three cells per cascaded power converter and with a total equivalent switching frequency of 92.5 kHz. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) has become one of the most favored topologies in medium-voltage and high-voltage (HV) applications. However, it still suffers from some drawbacks, including a lot of sizeable capacitors, high conduction losses, and no dc-fault ride-through capability. To circumvent these issues, this article presents a modified MMC, namely hybrid-leg MMC (HL-MMC). HL-MMC integrates a pair of three-phase line-frequency commutated HV voltage source converters (VSC) to replace up to 40% MMC submodules (SMs), leading to lower cost and conduction losses. Due to the ripple energy cancellation in the three-phase HV VSCs, the total energy storage requirement in HL-MMC could be also reduced, leading to up to 30% energy storage capacitance reduction compared with MMC. In addition, by combing the dc hybrid circuit breaker, the HV VSCs in the proposed HL-MMC also help provides the dc fault blocking capability, enabling a dc-fault tolerant HL-MMC without using the full-bridge (FB) MMC SMs. Therefore, a significant device and loss saving can be attained compared with the traditional MMC with FB SMs. The detailed converter operational analysis, control method, high-voltage direct current simulation model, and scale-down prototype are provided to validate the effectiveness of proposed topology. [ABSTRACT FROM AUTHOR]

Superconducting Josephson junctions and quantum phase slip (QPS) junctions create various hybrid circuits combined with nonsuperconducting elements. Those circuits require a common analysis method to bridge the gap between superconducting and nonsuperconducting electronics. This article presents an electromagnetic-flux-distribution model to unify the analyses of superconducting and non-superconducting circuits. This model uses electric and magnetic fluxes as the variables to unify the definitions of circuit elements and circuit laws; it derives general circuit equations of the circuits viewed from both electric and magnetic fields, to depict their dynamics and duality principles. This method is demonstrated in the analyses of a Josephson junction circuit and its dual QPS junction circuit. It shows that Josephson junction circuits are the magnetic-flux distribution network tuned by the Josephson current, while QPS junction circuits are the electric-flux distribution network modulated by the QPS voltage. [ABSTRACT FROM AUTHOR]

This article presents an analytical method to predict the magnetic field of eccentric surface-mounted permanent magnet synchronous machine (SPMSM) by applying the hybrid magnetic circuit and subdomain method. Taking stator saturation into account, the surface current is appended to the stator coil conductor, which can generate a magnetomotive force (MMF) to compensate the MMF drop across the stator core. The rotor yoke saturation effect is modeled by increasing the air-gap length. To solve the problem resulted from rotor eccentricity in analytical analysis, an equivalent transformation method is given. The transformation principle is that the eccentric machine can be equivalent to a concentric one with redistributed PM remanence and armature current density. On this basis, the subdomain method is adopted to predict the magnetic field of the reestablished machine. The proposed analytical method is implemented and evaluated on the 6p/36s and 8p/12s SPMSM and exhibits good agreement with the FEM and experiment results. [ABSTRACT FROM AUTHOR]

To improve the consumption of renewable energy and to meet complex load demands. A model of a multi-terminal flexible DC distribution network with multiple overhead branch lines is constructed. Aiming at frequent non-permanent faults of overhead lines, a fast pilot protection scheme is proposed to cover the whole fault process. Using the hybrid DC circuit breaker (HDCCB) action as the boundary mark, the fast pilot protection can be divided into two phases: post-fault and fault restart. The first phase highlights rapidity, sending a trip command to HDCCB within 1-2 ms after the fault. The second stage emphasizes reliability, and points out that the data of the whole fault process should be fully utilized, and to fully excavate the characteristics of fault current. A multi-time scale and multi-criteria fusion protection scheme is proposed, which can effectively improve the reliability of fault area identification. Finally, a corresponding model was built based on PSCAD, a large number of simulation tests and robustness analysis proved that the proposed fast pilot protection scheme is feasible. [ABSTRACT FROM AUTHOR]

To improve the reliability of power supply, reclosing schemes are required after transient faults, which commonly occur in overhead line based high voltage DC (HVDC) systems. However, in the event of permanent faults, the auto-reclosing scheme may cause a severe strike. To avoid the severe impacts caused by permanent faults, the fault type should be discriminated before activating the reclosing scheme. Therefore, an adaptive reclosing scheme based on phase characteristics is proposed in this paper. Firstly, the modulation of a periodic voltage by actively controlling the hybrid DC circuit breaker (DCCB) is introduced. Then, a cascaded π equivalent model and its decoupling algorithm are presented to analyze the frequency-domain characteristics of the measured impedance of the coupled overhead lines. From the frequency-domain characteristics, the frequency of the periodic detecting voltage is determined to analyze the phase features of the measured impedance at primary frequency. The permanent or transient faults can thus be accurately identified by using these different phase characteristics, with negligible influence on the healthy lines. In addition, the proposed scheme is robust to various fault resistances, leading to improved reliability. The effectiveness of the proposed scheme is verified in PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

It has been widely accepted to apply dc circuit breakers (DCCBs) to protect dc grids. Nevertheless, existing DCCBs have one or more following limitations: insulation recovery scheme of mechanical switch, additional precharge power supply, high conduction loss, unreliable current-breaking process, and unidirectional design. In this letter, a new DCCB with low conduction loss, simple precharging scheme, and reliable breaking ability is proposed. The proposed DCCB could break both fault and operating current actively with the same simple operation sequences. Moreover, bidirectional topology possessing all advantages mentioned previously is also presented. Topology introduction, parameters designing, and scaled-down experiment of the proposed DCCB are all presented in the letter. [ABSTRACT FROM AUTHOR]

Current-induced domain wall motion (CIDWM) shows promising prospects with low power, high density, high speed, and so on. Recent studies have demonstrated that magnetic tunnel junction (MTJ) based on CIDWM has great potential in mimicking a non-volatile artificial neuron and synapse. By combining the effect of the interfacial Dzyaloshinskii–Moriya interaction (DMI) to stabilize the Néel-type domain wall (DW) and the high-speed low-power advantages of spin orbit torque (SOT), the novel MTJ device is experimentally demonstrated with low threshold current and high propagation speed, which shows potential applications in the field of the artificial neuron and synapse. In this article, a compact model for CIDWM-MTJ based on SOT and DMI is presented. The model integrates the SOT mechanism for magnetization reversal and DW nucleation, CIDWM behaviors, and tunnel resistance theory of MTJ nanopillar. The micromagnetic simulation and the temporal evolution of the DW position are implemented by solving the Landau–Lifshitz–Gilbert (LLG) equation and the 1-D model. Based on the developed model, a hybrid CIDWM-MTJ/CMOS circuit is simulated for verification. The presented model combines the CIDWM dynamics and the MTJ magnetic dynamics, showing potential application for the simulation of all-spin artificial neural network (ANN). [ABSTRACT FROM AUTHOR]

The design and development of a hybrid Gaussian pulse radar transceiver, including transmitter and receiver, is presented. The transmitter is realized using a transistor-based square pulse generator, a tunable step recovery diode (SRD) Gaussian pulse-shaping network, and a differentiator. The SRD circuit design is modified using a high-pass filter to have a low ringing and narrow pulsewidth. The output pulse with a broadband amplifier has a power of 500 mW, at a pulse repetition frequency (PRF) of 10 MHz, and tunable pulsewidth ranges from 56 to 300 ps. A 90° coupler is configured to convert the Gaussian pulse into a monopulse. Then, a transmitter antenna is used to radiate the pulse, and a separate receiving antenna is used to receive the reflected pulse. The receiver is comprised of a local Gaussian pulse generator, a radio frequency mixer (RF-mixer) accompanied by a low-pass filter (LPF), a low-frequency amplifier (LFA), and an analog-to-digital converter (ADC). The RF-mixer is used for expanding the receiving pulse from the receiving antenna by a factor of 100000. The LPF and LFA are used to detect the envelope of the output of the RF-mixer and amplify it. The ADC is interposed between the LFA and a processor to digitize the expanded pulse for data processing. The validity and reliability of the digitized expanded pulse compared to those received using a sampling oscilloscope are 93% in agreement, which is remarkable. A version of the system is also developed for a single-antenna operation by utilizing an ultrawideband (UWB) coupler as a semicirculator. Both the systems are compared, and the benefits of each are illustrated. The flexibility and performance of the designs are analyzed. The proposed system demonstrates subcentimeter imaging capabilities. [ABSTRACT FROM AUTHOR]

The physically unclonable function (PUF) has been implemented with circuits that perform amplification of randomly given small process mismatch by using an explicit amplifier or by making a signal path repeatedly experience the same delay skew in an oscillator. Though the amplifier approach provides a fast response, it is vulnerable to noise at the first stage of amplification. On the other hand, the oscillator-based scheme requires a longer time to develop a digital output while achieving good noise immunity. This article proposes a PUF circuit exploiting a hybrid architecture, which combines a process skew amplification scheme in an oscillator collapse topology. The proposed scheme compensates for the drawbacks of the two approaches while achieving merits of them, i.e., high sensitivity to process variation and good immunity to noise. The supply rails of an even-stage ring oscillator (RO) are alternately fed from a diode-based threshold-sampling block. An IC with an array of 128 PUF cells is fabricated in 40-nm CMOS, showing a native bit error rate (BER) of 0.027%. Processing of 7-b temporal majority voting (TMV7) with a 3.64% masking demonstrates an error-free operation in a nominal condition. It shows a BER of 0.0019% in the worst condition under a voltage range of 0.7–1.4 V and a temperature range of −40 °C to 125 °C. [ABSTRACT FROM AUTHOR]

This article aims to investigate the limitations on the amplitude of the conventional step recovery diode (SRD)-based Gaussian pulse transmitter and techniques to overcome the limits. The operation of the modified design is examined and compared with a conventional configuration. The results show a considerable increase in the pulse amplitude. The high pulse amplitude of the modified configuration represents an increase in the transmitter’s output power and its improved probing range. The Gaussian pulse is converted into the first derivative Gaussian pulse using a 90° broadband coupler as a differentiator and a semi-differentiator delay line circuit with balanced stubs. The output monopulse generated using the balanced stub delay line has more symmetric sidelobes with narrower pulsewidth than the 90° couplers. Experimental results have shown the high performance of the proposed transmitter over the conventional designs in terms of pulse amplitude and symmetry. [ABSTRACT FROM AUTHOR]

The reliability of meshed DC grids mainly relies on their ability in DC fault protection and line power flow managing. Multiple DC circuit breakers (DCCB) and current flow controller (CFC) need to be installed, which significantly increases the system cost. A novel current flow controller integrated with hybrid dc circuit breaker (CFC-IHCB) is proposed to significantly reduce the loss and cost of the whole system. Only one unidirectional IGBT string based main breaker branch is needed for n lines, and the CFC function is integrated into the load communication switches (LCSs). The basic working principle of proposed topology is presented and analyzed. The functionality is verified and a comparison of the proposed solution and other DCCB/CFC solutions is given based on a multi-terminal HVDC system case study. [ABSTRACT FROM AUTHOR]

A new series-type hybrid circuit breaker (S-HCB) concept for dc fault protection is reported that is fundamentally different from other prior-art hybrid circuit breakers (HCB) or solid-state circuit breakers (SSCB) in the literature. The S-HCB conducts its load current through metal wires instead of power semiconductor switches and curtails its fault current to near zero throughout the entire opening process of a series mechanical switch. It offers the low on-resistance of the conventional mechanical contacts for normal operation and µs-scale fault response even faster than the fast-acting SSCBs. A proof-of-concept S-HCB prototype experimentally demonstrates the interruption of a fault current of 30 A within 10 μs at a dc voltage of 600 V. The operating principle, simulation, and experimental results are discussed in this letter. [ABSTRACT FROM AUTHOR]

In this article, metal oxide varistor (MOV) design optimization and switching control in the main circuit breaker (MCB) branch of a progressively switched hybrid dc circuit breaker (DCCB) is presented. A progressively switched hybrid DCCB can achieve faster fault isolation with reduced peak fault current magnitude and transient recovery voltage compared with a regular hybrid DCCB due to its modified switching strategy. Consequently, thermal stress on the semiconductor devices in MCB is significantly reduced. Analytical model of the system dynamics during fault isolation with progressive switching is derived to demonstrate the switching scheme’s effect on the energy-absorbing component, MOV, during turn-off process. Derived analytical model in conjunction with the displacement curve of the fast mechanical switch of the hybrid DCCB is utilized to optimize the components of the main circuit breaker branch to reduce MOV degradation through asymmetric energy dissipation. A model of the circuit breaker is built in PSCAD to validate the performance of the proposed optimization method in a 10-kV/250-A system with four stage progressive switching. Additionally, a low voltage system model at 380 V is developed in PLECS for two stage progressive switching that works as the basis of experimental validation. This includes both lookup table-based MOV model and device thermal model for junction temperature estimation. Experimental results are provided for a 380-V system to demonstrate reduced fault current peak in a progressive switching and near uniform energy absorption in optimally selected MOVs. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) high-voltage direct current (HVdc) transmission is a promising method to integrate renewable energies. However, limiting the dc-link fault current and accelerating the fault-current clearance are critical issues for MMC-HVdc systems. In this article, we propose an air-core-transformer-based fault-current limiter (ACT-FCL) in cooperation with the dc circuit breaker to limit fault-current rising and decrease fault-clearing time. Compared with the conventional dc reactor, hybrid current-limiting circuit, current-commutation-based fault-current limiter (FCL), and magnetic coupling FCL, the ACT-FCL can increase the equivalent inductance during the dc fault stage to reduce the rising rate and peak of fault current. The ACT-FCL can also decrease the equivalent inductance during the fault-current-clearing stage to reduce the fault-clearing time. The simulations and laboratory experiments verify the effectiveness of the proposed ACT-FCL in the bidirectional HVdc systems. The ACT-FCL may be extended to more fields, such as dc microgrid and domestic dc transmission. [ABSTRACT FROM AUTHOR]

The hybrid dc circuit breaker (HDCCB) is one of the most promising solutions for the dc interruption. But the power electronics-based load commutation switch (LCS) in the main current path causes the high on-state loss and cost, which inhibits the application of the HDCCB. In this paper, a novel hybrid dc circuit breaker is proposed, in which the vacuum interrupter with the external transverse magnetic field (ETMF) is designed to improve the arc voltage and thus enhance the current commutation to power electronics. The ETMF-based vacuum interrupter achieves the fast current commutation instead of the LCS, which realizes the low on-state loss and cost while preserving the short commutation and interruption time. The arc voltage characteristic with ETMF is analyzed, and the influence of the different factors on the commutation time and di/dt before current zero are investigated in detail. Based on the calculation results, a 10 kV dc breaker prototype based on the proposed topology is developed with the breaking current of 15.5 kA. Finally, the application of the proposed scheme in HVdc grids is discussed. [ABSTRACT FROM AUTHOR]

In this paper, a novel asymmetric-permanent- magnet hybrid-magnetic-circuit variable flux memory machine (AH-VFMM) is proposed. The low coercive force (LCF) permanent magnets (PMs) are located on one biased side of the hybrid magnetic circuit branch, forming an AH configuration. Compared to its conventional symmetric-PM hybrid-magnetic-circuit (SH) counterpart, the proposed design benefits from the reduced usage of high coercive force (HCF) rare-earth magnet, alleviating the magnetic saturation to improve the flux regulation (FR) range, while the excellent load demagnetization withstand (LDW) capability can be still maintained. The topology evolution and operating principle of the proposed machine are introduced and described, respectively. Then, based on the combination of the magnetic equivalent circuit (MEC) method and Schwarz-Christoffel (SC) transformation, a hybrid analytical model is established to quantitatively reveal the mechanism of FR range extension, and facilitate the initial design of the machine. The electromagnetic characteristics of the proposed machine under different magnetization states (MSs) are investigated and compared with those of the conventional SH counterpart. Finally, an AH-VFMM prototype is manufactured, and the experimental measurements are carried out to verify the validity of the proposed design. [ABSTRACT FROM AUTHOR]

The hybrid dc circuit breaker is one of the most promising dc circuit breakers (DCCBs). However, its cost is relatively high, and the completion of its fault isolation is significantly delayed because of the large current limiting inductors configured in the multiterminal dc grid. Besides, due to the utilization of overhead lines, the probability of temporary faults is much increased, which means there is a great possibility that the power supply can be rapidly restored by reclosing DCCBs. However, the temporary faults must be distinguished from the permanent faults before the reclosing operation to avoid damaging the fragile power electronic equipment. Therefore, considering the above issues, a novel multiport hybrid dc circuit breaker (MHCB) is proposed in this article. The MHCB mainly has three advantages: the reduced implementation cost by sharing the expensive main breaker among multiple lines, the reduced fault isolation time by bypassing the current limiting inductor during energy dissipation, and the ability to reclose softly. Extensive simulations and experiments verify the effectiveness of the device. In addition, the comparison of the new device and existed solutions is presented. [ABSTRACT FROM AUTHOR]

Flexible DC grids with dedicated metallic return (DMR) encounter two major challenges when reclosing hybrid DC circuit breakers (DCCBs): (1) identifying permanent and nonpermanent faults to determine whether DCCBs should be reclosed; and (2) identifying pole-to-ground (P-GND) and pole-to-DMR (P-DMR) faults to determine whether all DC lines should be isolated when a permanent fault occurs. Under a permanent P-DMR fault, all DC transmission lines should be isolated instead of maintaining half of the power transmission. In this study, the equivalent circuits and analytical expressions of the fault currents under the P-GND and P-DMR faults are deduced. On this basis, two different criteria are proposed to discriminate these two faults. Permanent and nonpermanent faults are recognized according to the characteristics of the residual voltage of the DC transmission line. Finally, a comprehensive reclosing strategy considering fault type discrimination for a hybrid DCCB is developed. A simulation model of a four-end flexible HVDC grid with DMR is constructed in PSCAD/EMTDC. The validity of the proposed reclosing strategy is verified through different simulation cases. [ABSTRACT FROM AUTHOR]

Hybrid dc circuit breakers (HCBs) are recognized as suitable devices for protecting high-voltage direct-current (HVDC) systems, along with other dc circuit breakers (DCCB). However, compared to mechanical circuit breakers, HCBs exhibit higher conduction losses. Such losses are inevitable under no-fault conditions as current may flow through some of the semiconductor switches. An integrated circuit breaker (ICB) minimizing these losses is presented in this paper, and this is achieved by replacing semiconductor switches by mechanical components in the current path. For completeness, the topology design, operating sequence and a mathematical analysis for component sizing of the device are provided. In addition, an estimation of the conduction losses is quantified. It is estimated that the power losses of an ICB are 2 to 30% of an HCB only. The ICB has been implemented in PSCAD/EMTDC to demonstrate its effectiveness for isolating dc faults, with simulations conducted on a three-terminal HVDC grid. [ABSTRACT FROM AUTHOR]

This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a four-level pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide frequency range. Prototyped in a 28-nm CMOS, the proposed BBCDR occupies a tiny area of 0.0285 mm2 and exhibits a 23-to-29-Gb/s capture range. The acquisition speed [8.2 Gb/s/ $\mu \text{s}$ ] and energy efficiency (0.68 pJ/bit) compare favorably with the state of the art. [ABSTRACT FROM AUTHOR]

The 6-in gate commutated thyristor (GCT) is suitable for hybrid dc circuit breaker (HDCB) application with its large chip area and high maximum controllable current (MCC), compared with traditional 4-in GCTs. P+ base doping dispersion control is of vital importance in the 6-in GCT chip. Based on the strong correlation between P+ base doping and the gate-cathode breakdown voltage (${V}_{\text {gbr}}$), P+ base doping dispersion is characterized through ${V}_{\text {gbr}}$. Test results show that ${V}_{\text {gbr}}$ dispersion in the 6-in GCT sample with etched depth of around $10~\mu \text{m}$ is about 2 V with the average ${V}_{\text {gbr}}$ of around 22 V. While ${V}_{\text {gbr}}$ dispersion in the sample with etched depth of above 20 $\mu \text{m}$ is above 6 V with the average ${V}_{\text {gbr}}$ of around 27 V. These are consistent with the 2-D simulation results. Then, P+ base doping parameter design is optimized through experiment. Both turn-on and turn-off characteristics of 6-in GCT samples with different P+ base doping parameter designs are compared with HDCB application. The final optimized 6-in GCT chip has no difficulty in turning on under a low dc-link voltage below 100 V and it can turn off 13 kA with the overvoltage of about 4.5 kV successfully, which shows potential in HDCB application. [ABSTRACT FROM AUTHOR]

Nearest neighbor (NN) search is widely used in pattern classification and memory-augmented neural networks. To overcome the von Neumann bottleneck in conventional NN search architecture, in this study, nanoelectromechanical-switch-based ternary content-addressable memory (NEMTCAM) is introduced for the NN classifier. NEMTCAM can calculate the Hamming distance between the input vector and the stored vectors in a parallel search operation. The NEMTCAM operation was experimentally demonstrated. Furthermore, an analytical model for NN search accuracy, including cell-to-cell parasitic resistance, is presented. NEMTCAM can calculate up to 10 Hamming distances in 32-bit words owing to the high current ratio of the NEM memory switches. [ABSTRACT FROM AUTHOR]

Nanoelectromechanical (NEM) switches offer the advantages of zero OFF-state leakage current, abrupt switching characteristics, nonvolatile (NV) operation, and relatively low ON-state resistance as compared with CMOS transistors predominantly used for digital computing today. NEM switches can be implemented using metallic interconnect layers formed in the back-end-of-line (BEOL) steps of a standard CMOS IC manufacturing process, in order to enable compact implementation of hybrid CMOS-NEM circuits. In this article, a release-etch method is developed for realizing BEOL NV-NEM switches with $\leq 100$ -nm contact gaps. A functional array of BEOL NV-NEM switches is used to implement a hybrid CMOS-NEM IC for data search applications. NV-NEM switch design optimization to minimize the programming voltage and accelerate switching speed is discussed. A scaled NV-NEM technology is projected to be advantageous for high-speed, low-power reconfigurable computing applications. This projection is validated with experimental data for a BEOL NV-NEM switch implemented with a conventional 16-nm CMOS IC manufacturing process. [ABSTRACT FROM AUTHOR]

Long pulse gas lasers utilizing double-discharge circuits are different from the single-short pulse gas lasers in that they do not require all of the desired energy to be deposited into the peaking capacitors prior to ignition of the main gap. Instead, the majority of the energy is held in another capacitor that is then discharged in the form of a longer duration discharge pulse output compared with that of single-short pulse lasers. Extended stability of the discharge is typically achieved by igniting the main gap discharge at higher ignition voltages. Several double-discharge circuit topologies exist in the literature. However, each topology has its own disadvantages primarily centered around the components needed and the resulting complexity. In this article we introduce the application of the new hybrid circuit pulsed power topology as a double-discharge circuit with high ignition voltages. The hybrid circuit pulsed power topology was originally published by the authors of this article in their previous publication titled “A New Hybrid Pulsed Power Circuit Topology for Gas Laser Applications.” The advantage of the hybrid circuit as a double-discharge circuit is that it does not require any special device [e.g., semiconductor opening switch (SOS) diode] and can use commonly available components. [ABSTRACT FROM AUTHOR]

Autonomous-driving features necessitate a fault-tolerant (FT) power-management unit in 48-V automotive applications. This article presents a monolithic single-phase closed-loop masterless FT four-to-one hybrid Dickson converter IC for high-conversion-ratio 48-V automotive multi-phase applications. The chip includes: 1) a mixed-signal droop-based valley-current ON-time quasi-fixed-frequency control, which enables masterless multi-phase operation capability; 2) single-point short-circuit fault and open-circuit fault detection and blocking of any power switches or flying capacitors; 3) an optimized high-voltage (HV) power stage with fully integrated flying-capacitor-sourced gate drivers without any external bootstrap capacitors; 4) a glitch-free cross-coupled bootstrapped HV level shifter; and 5) a dual-leg bidirectional closed-loop current-sensing circuit optimized for the hybrid Dickson topology. The design was fabricated in a 0.13- $\mu \text{m}$ 90-V automotive silicon-on-insulator (SOI) bipolar-CMOS–DMOS (BCD) process. The measured results confirm the operation over 20–60-V input, 3.3-V nominal output, 3-A maximum load, and 320-kHz effective switching frequency within the automotive-grade −40 °C–+125 °C ambient temperature. The design achieves above 90% measured efficiency at maximum conversion ratio and load at room temperature. A three-phase system is used to evaluate and confirm the fault-blocking capability and continuous power delivery upon detection of a fault. [ABSTRACT FROM AUTHOR]

Hybrid ac-dc grids can gain the benefits of both ac and dc grids. The Ac-Dc circuit analysis can be performed using sequential methods that decouple ac and dc systems or unified (simultaneous) methods that solve the ac and dc mismatch equations simultaneously. This paper introduces a unified ac–dc analysis via an improved model for the ac–dc coupling through which the ac and dc load flow analyses can be simultaneously conducted. The ac–dc coupling is modeled by an admittance building block, and thus, the dc grid is converted to an ac-equivalent circuit within the hybrid network. However, unlike past literature, state variables beyond nodal voltages and angles are avoided, leading to a simpler algorithm, and reactive power injection of the coupling mechanism, a requirement for the IEEE 1547 Std, is explicitly modeled. Furthermore, the proposed model can be applied to both voltage-source and line-commuted converters. Accordingly, the conventional ac power flow algorithms can be applied to the hybrid circuit paving the path for seamless adoption of hybrid circuits and significantly saving time and effort in programming, troubleshooting, and upgrading techniques currently used in research and industry as well as a high-level analysis tool regarding the hybrid ac-dc grid is achieved. [ABSTRACT FROM AUTHOR]

Two key challenges in meshed multi-terminal dc (MTdc) grids are line power flow management and fault current interruption, which can be solved by current flow controllers (CFCs) and hybrid dc circuit breakers (HCBs), respectively. However, the power losses and the implementation costs of CFCs and HCBs are relatively high. In order to overcome these drawbacks, a combined HCB (CHCB) is proposed in this article by fully utilizing the core ideas of the interline dual H-bridge CFC and the HCB. The proposed device can substitute multiple HCBs at a dc bus with greatly reduced cost. In addition to the fault current interruption capability, the current flows in the adjacent lines can be controlled by the embedded multi-line CFC in the CHCB expanded from the existing interline dual H-bridge CFC. The system-level behavior of the proposed CHCB is similar to the separate solution of the typical HCB and the multi-line CFC. Extensive simulations and experiments verify the effectiveness of the proposed device. Besides, a comparison of the proposed CHCB and the separate solution is presented. [ABSTRACT FROM AUTHOR]

The diode bridge submodule (SM) is one of the basic units of a hybrid high-voltage dc circuit breaker. This article works on the low inductance design of a single SM and series SMs. For the layout design of a single SM, this article proposes a simple and clear +-shaped SM layout, the low inductance design is simplified to the optimization of two laminated busbars with a simple structure. Based on the +-shaped SM layout, this article further proposes an SM structure with holes in diodes region, the stray inductance is further reduced, and only one integrated laminated busbar is needed in a single SM. For the layout design of series SMs, this article makes full use of the layout of a single SM and the mutual inductances between the SMs, series SMs are alternately connected in reverse. The single SM layout proposed in this article is effective in reducing the stray inductance. The loop stray inductance in stage II reduced from 148.4 to 72.3 nH, a 51.3% reduction. When the two parallel IGBTs turn off a 6 kA fault current in 2 μs, the voltage spike is reduced from 786.1 to 423.4 V, a 46.1% reduction. And the stray inductance difference of the bidirectional current path is controlled to about 10 nH. The layout of series SMs proposed in this article is effective in reducing the length of the series SMs, the length is reduced by 16.7%. The experimental results show that the SMs layout proposed in this article is effective. [ABSTRACT FROM AUTHOR]

Prognosis of discrete component with intermittent fault in hybrid systems is challenging since the component has only two states (i.e., ON and OFF) and no associated physical parameter in the model can quantify the degradation. This article aims to solve the discrete component prognosis problem under the model-based paradigm. First, the fault detection and isolation module help find the possible faulty discrete components. Based on the isolated possible faulty discrete components, Levy flight biogeography-based optimization is proposed to identify the faulty discrete component states, as well as the fault appearing and fault disappearing instants. Second, a Weibull function-based degradation model which can capture the duration evolution of intermittent fault of discrete component in observation window (OW) is developed using coordinate reconstruction approach, and the degradation model coefficients can be calculated from the fault identification results. After that, the concept of failure threshold for faulty discrete component is defined based on the ratio of fault duration to OW, which enables the prognosis of intermittent fault in discrete component. Finally, the proposed methodologies are validated by experiment results. Note to Practitioners—This article is motivated by the intermittent fault prognosis problem of discrete components (e.g., relays and hydraulic valves) in hybrid systems. Existing fault prognosis researches do not consider discrete component which is an important part of hybrid systems. For the intermittent fault prognosis of discrete component, the observation window (OW) concept and coordinate reconstruction (CR) method are proposed to establish the degradation model, and the ratio of fault duration to OW is used to define the failure threshold of discrete component. To show the effectiveness of the proposed methods, an application on a hybrid circuit system is considered. It is noted that the degradation pattern (e.g., increase of frequency or duration of intermittent fault) of discrete components may vary in different systems, while the degradation process can be quantified by the OW and CR methods developed in this article, which enables the prognosis of intermittent fault in discrete component for various hybrid industrial systems. The proposed approach can be applied to industrial hybrid systems if the following conditions are satisfied: 1) the hybrid bond graph model of the monitored system can be established, based on which the fault detection and isolation can be implemented and 2) the monitored system contains multiple discrete components suffering from intermittent faults whose appearing and disappearing instants can be identified by certain method. [ABSTRACT FROM AUTHOR]

A major decision surrounding the design of pulsed power circuits for gas lasers is the choice between a thyratron and solid-state switches. The thyratron is a mature device technology whose cost is increasing. The ratings of solid-state switches still do not match those of a thyratron. Pulse transformer and pulse compression circuits must be added to overcome the lower ratings of solid-state switches leading to a higher parts count and cost. This article proposes a new solid-state pulse power topology called the hybrid circuit topology to address the parts count and cost issue. The hybrid circuit makes use of a combination of capacitive and inductive energy storage to reduce the time required to transfer the energy from the transformer primary to the secondary side. This ultimately reduces the quantity of magnetic material used in the pulse compression circuit. [ABSTRACT FROM AUTHOR]

Hybrid circuit breaker (HCB) has shown good performance for interrupting dc fault current. However, a massive number of IGBTs in series is needed. These will lead to high costs and significant difficulty in balancing IGBT dynamic voltage. This paper proposes a bidirectional hybrid circuit breaker based on a cascaded half-bridge submodule structure to reduce the overall costs and implementation difficulty of HCB. The number of IGBTs is reduced by 50%, and the operating speed is fast enough. A model of a four-terminal modular multilevel converter (MMC) system with a proposed hybrid circuit breaker in different stages is developed to describe the fault blocking process more clearly. The performance of the proposed HCB is validated and compared with other HCB structure through both theoretical derivation and time-domain simulation. [ABSTRACT FROM AUTHOR]

Medium voltage direct current (MVDC) power systems are in their early phase of development, but the lack of efficient and reliable DC circuit breakers is currently one of the most significant bottlenecks for widespread adoption of MVDC applications. Compared to protection devices in high voltage direct current (HVDC) systems, MVDC circuit breakers are expected to interrupt fault currents with higher rates of rise in more power-dense and more controllable structures. A hybrid approach with a piezoelectrically actuated fast mechanical switch in parallel to a solid-state circuit breaker is expected to meet the above requirements. A prototype of a 15 kV-class piezoelectrically actuated fast mechanical switch is presented in this paper. The prototype demonstrates an actuator opening time of 1 ms, a breakdown voltage of over 20 kV, and a continuous current rating of 500 A. After integrating the fast mechanical switch into a hybrid circuit breaker testbed, the fast mechanical switch was able to open within 1.5 ms and the fault was cleared within 5 ms. Therefore, piezoelectrically actuated fast mechanical switches can enable fast, reliable and controllable protection for various MVDC systems like electric ships, electric aircraft and microgrids that integrate distributed energy resources. [ABSTRACT FROM AUTHOR]

A mechanical switch can be used instead of a power electronic load commutation switch in orderto reduce the losses during normal power flow in standard hybrid DC circuit breakers. The success of current commutation in such hybrid breakers depends on the arc voltage formed across the contacts in the mechanical switch. The behaviour of rapidly elongated, wall constricted arcsgenerated during the opening of an ultra-fast mechanical switch in the air is studied here. The voltage-current characteristics of the generated arcs are obtained for steady state contact opening velocities of 6, 11 and 21 m/s. It is found that the arc voltage at a given current and contact separation increases with the contact opening velocity. It is shown that stationary,zero-contact-velocity characteristics can not be used to accurately quantify the voltage build-up in fast elongating arcs in hybrid breakers. A best-fitting black-box equation for the dynamic arc characteristics is presented for the tested velocities. The obtained voltage-current characteristics are used as input to simulate the current commutation process in a 12 kV hybridDC circuit breaker case-study. Different scenarios of current commutation failure related to the arc voltage build up are identified. It is shown that these failures scenarios can be avoided by increasing the contact opening velocity. [ABSTRACT FROM AUTHOR]