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Nuclear instruments & methods in physics research / A 1006, 165396 (2021). doi:10.1016/j.nima.2021.165396, The CLIC Tracker Detector (CLICTD) is a monolithic pixel sensor. It is fabricated in a 180 nm CMOS imaging process, modified with an additional deep low-dose n-type implant to obtain full lateral depletion. The sensor features a small collection diode, which is essential for achieving a low input capacitance. The CLICTD sensor was designed as a technology demonstrator in the context of the tracking detector studies for the Compact Linear Collider (CLIC). Its design characteristics are of broad interest beyond CLIC, for HL-LHC tracking detector upgrades. It is produced in two different pixel flavours: one with a continuous deep n-type implant, and one with a segmented n-type implant to ensure fast charge collection. The pixel matrix consists of 16 �� 128 detection channels measuring 300 ��m �� 30 ��m. Each detection channel is segmented into eight sub-pixels to reduce the amount of digital circuity while maintaining a small collection electrode pitch. This paper presents the characterisation results of the CLICTD sensor in a particle beam. The different pixel flavours are compared in detail by using the simultaneous time-over-threshold and time-of-arrival measurement functionalities. Most notably, a spatial resolution down to (4.6��0.2) ��m is measured. A time resolution down to (5.8��0.1) ns is observed, after applying an offline time-walk correction using the pixel-charge information. The hit detection efficiency is found to be well above 99.7 % for thresholds of the order of several hundred electrons., Published by North-Holland Publ. Co., Amsterdam

International audience; The monolithic CMOS pixel sensor for charged particle tracking has already become a mainstream technology in high energy particle physics (HEP) experiments. During the last decade, progressive improvements have been made for CMOS pixels to deal with the high-radiation and high-rate environments expected, for example, at the future High Luminosity LHC. One of the key ingredients of these improvements is to achieve a fully depleted sensitive layer, where the charge collection is guided by strong drift field lines. CMOS sensors incorporating such charge collection property, often referred to as DMAPS (Depleted Monolithic Active Pixel Sensor), have been recently demonstrated in several large-scale monolithic prototypes with integrated fast readout architectures. This contribution summarizes the recent progress made on the large-scale DMPAS development, focusing on two demonstrator chips designed in the LFoundry 150 nm and the TowerJazz 150 nm CMOS processes, namely LF-Monopix1 and TJ-Monopix1.

This is part of a document, which is devoted to the developments of pixel detectors in the context of the International Linear Collider. From the early developments of the MIMOSAs to the proposed DotPix I recall some of the major progresses. The need for very precise vertex reconstruction is the reason for the Research and Development of new pixel detectors, first derived from the CMOS sensors and in further steps with new semiconductors structures. The problem of radiation effects was investigated and this is the case for the noise level with emphasis of the benefits of downscaling. Specific semiconductor processing and characterisation techniques are also described, with the perspective of a new pixel structure., Comment: report preprint March 2020

The planned luminosity increase at the Large Hadron Collider in the coming years has triggered interest in the use of the particles' time of arrival as additional information in specialized detectors to mitigate the impact of pile-up. The required time resolution is of the order of tens of picoseconds, with a spatial granularity of the order of 1 mm. A time measurement at this precision level will also be of interest beyond the LHC and beyond high energy particle physics. We present in this paper the first developments towards a radiation hard Depleted Monolithic Active Pixel Sensor (DMAPS), with high-resolution time measurement capability. The technology chosen is a standard high voltage CMOS process, in conjunction with a high resistivity detector material, which has already proven to efficiently detect particles in tracking applications after several hundred of Mrad of irradiation., Comment: 14 pages, 11 figures

12th International 'Hiroshima' Symposium on the Development and Application of Semiconductor Tracking Detectors, HSTD12, Hiroshima, Japan, 14 Dec 2019 - 18 Dec 2019; Nuclear instruments & methods in physics research / A 981, 164520 (2020). doi:10.1016/j.nima.2020.164520, Monolithic silicon sensors developed with High-Voltage CMOS (HV-CMOS) processes have become highly attractive for charged particle tracking. Compared with the standard CMOS sensors, HV-CMOS sensors can provide larger and deeper depletion regions that lead to larger signals and faster charge collection. They can provide high position resolution, low material budget, high radiation hardness and low cost that are desirable for high performance tracking in harsh collision environment. Various studies have been conducted to explore the technology feasibility for the large-area tracking systems at future collider experiments., Published by North-Holland Publ. Co., Amsterdam

International audience; The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Custom built pixel sensors, their readout electronics and the detector mechanical structure are described in detail. Selected detector design aspects and production steps are presented. The detector operations during the three years of data taking (2014–2016) and the overall performance exceeding the design specifications are discussed in the conclusive sections of this paper.

The upgrade of the tracking detectors for the High Luminosity-LHC (HL-LHC) requires the development of novel radiation hard silicon sensors. The development of Depleted Monolithic Active Pixel Sensors targets the replacement of hybrid pixel detectors with radiation hard monolithic CMOS sensors. We designed, manufactured and tested radiation hard monolithic CMOS sensors in the TowerJazz 180 nm CMOS imaging technology with small electrodes pixel designs. These designs can achieve pixel pitches well below current hybrid pixel sensors (typically 50 × 50 μ m ) for improved spatial resolution. Monolithic sensors in our design allow to reduce multiple scattering by thinning to a total silicon thickness of only 50 μ m . Furthermore monolithic CMOS sensors can substantially reduce detector costs. These well-known advantages of CMOS sensor for performance and costs can only be exploited in pp-collisions at HL-LHC if the DMAPS sensors are designed to be radiation hard, capable of high hit rates and have a fast signal response to satisfy the 25 ns bunch crossing structure of LHC. Through the development of the MALTA and Mini-MALTA sensors we show the necessary steps to achieve radiation hardness at 1 0 15 n e q /cm2 for DMAPS with small electrode designs. The sensors combine high granularity (pitch 36.4x 36 . 4 μ m 2), low detector capacitance ( 5fF/pixel) of the charge collection electrode ( 3 μ m ), low noise (ENC ≈ 10 e − ) and low power operation (1 μ W/pixel) with a fast signal response (25 ns bunch crossing). The sensors feature arrays of 512 × 512 (MALTA) and 16 × 64 (Mini-MALTA) pixels. To cope with high hit rates expected at HL-LHC ( > 200 MHz/cm2) we have implemented a novel high-speed asynchronous readout architecture. The paper summarises the optimisation of the pixel design to achieve radiation hard pixel designs with full efficiency after irradiation at > 98% after 1 0 15 n e q /cm2).

International audience; The physics case of the International Linear Collider (ILC) is intended to encompass detailed studies of the Higgs boson and top-quark sectors as well as of fermion-pair production, complemented with direct searches for BSM physics manifestations. All these components of the physics programme involve flavour specific dynamical content, which calls for unprecedented performances of the charged particle detectors composing the experiments, special attention being devoted to the possibility to achieve ambitious flavour tagging performances. The latter benefit from the moderate radiation tolerance and read-out speed required, combined with the possibility to exploit the machine duty cycle for power saving, to achieve thereby a spatial resolution per detector layer of a few micrometres in both directions, combined with a material budget not exceeding 0.15 % of radiation length.Since the delivery of the ILC TDR IN 2012/13, substantial progress was achieved to develop a vertex detector fully suited to the physics requirements. Several pixel sensor approaches were followed, both from the technological and from the read-out architecture points of view. They are motivated by the capability to suppress the impact of beam related background, which dominates the hit density of the vertex detector, and tends to grow as the luminosity of the ILC is being upgraded to 4 to 6 times the baseline values. The paper summarises the performances achieved as well as the status and the perspectives of the different approaches. It shows that the possibility opens up to realise single bunch tagging with square pixels featuring less than 20µ m pitch and associated to a power consumption compatible with air cooling.

Nuclear instruments & methods in physics research / A Accelerators, spectrometers, detectors and associated equipment Section A A931, 127 - 134 (2019). doi:10.1016/j.nima.2019.04.037, A study of 3D pixel sensors of cell size 50μm×50μm fabricated at IMB-CNM using double-sided n-on-p 3D technology is presented. Sensors were bump-bonded to the ROC4SENS readout chip. For the first time in such a small-pitch hybrid assembly, the sensor response to ionizing radiation in a test beam of 5.6 GeV electrons was studied. Results for non-irradiated sensors are presented, including efficiency, charge sharing, signal-to-noise, and resolution for different incidence angles., Published by North-Holland Publ. Co., Amsterdam

Two different depleted monolithic CMOS active pixel sensor (DMAPS) prototypes with a fully synchronous column-drain read-out architecture were designed and tested: LF-Monopix and TJ-Monopix. These chips are part of a R&D effort towards a suitable implementation of a CMOS DMAPS for the HL-LHC ATLAS Inner Tracker. LF-Monopix was developed using a 150nm CMOS process on a highly resistive substrate (>2 k$\Omega\,$cm), while TJ-Monopix was fabricated using a modified 180 nm CMOS process with a 1 k$\Omega\,$cm epi-layer for depletion. The chips differ in their front-end design, biasing scheme, pixel pitch, dimensions of the collecting electrode relative to the pixel size (large and small electrode design, respectively) and the placement of read-out electronics within such electrode. Both chips were operational after thinning down to 100 $\mathrm{\mu}$m and additional back-side processing in LF-Monopix for total bulk depletion. The results in this work include measurements of their leakage current, noise, threshold dispersion, response to minimum ionizing particles and efficiency in test beam campaigns. In addition, the outcome from measurements after irradiation with neutrons up to a dose of $1\times10^{15}\,\mathrm{n_{eq} / cm}^{2}$ and its implications for future designs are discussed., Comment: Proceedings of the PIXEL 2018 Workshop

International audience; In view of the LHC upgrade for the High Luminosity phase (HL-LHC), the ATLAS experiment plans to replace the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of thin 100 and 130μm n-in-p planar pixel sensors produced by FBK-CMM with active-edge technology in collaboration with LPNHE and INFN. Beam-test results are presented, with focus on the hit efficiency at the detector edge of a novel design consisting of a staggered deep trench.

International audience; In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The presentation describes the performance of novel n-in-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, some feedback from preliminary results of the first beam test will be discussed.

LF-Monopix1 and TJ-Monopix1 are depleted monolithic active pixel sensors (DMAPS) in 150 nm LFoundry and 180 nm TowerJazz CMOS technologies respectively. They are designed for usage in high-rate and high-radiation environments such as the ATLAS Inner Tracker at the High-Luminosity Large Hadron Collider (HL-LHC). Both chips are read out using a column-drain readout architecture. LF-Monopix1 follows a design with large charge collection electrode where readout electronics are placed inside. Generally, this offers a homogeneous electrical field in the sensor and short drift distances. TJ-Monopix1 employs a small charge collection electrode with readout electronics separated from the electrode and an additional n-type implant to achieve full depletion of the sensitive volume. This approach offers a low sensor capacitance and therefore low noise and is typically implemented with small pixel size. Both detectors have been characterized before and after irradiation using lab tests and particle beams., 7 pages, 8 figures. Proceedings of the 12th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors

International audience; Belle II detector upgrade is being discussed aiming to collect five times larger integrated luminosity of 250 ab−1. The beam background level is expected five times higher than current design, thus a new pixel vertex detector with faster readout should be developed. We have invented a new pixel detector concept DuTiP for the Belle II upgrade which can be also used for the International Linear Collider (ILC) with small modifications. To realize the DuTiP concept, an SOI technology is chosen as a baseline with a pixel size of 35μm×35μm. The DuTiP concept and its application to a monolithic pixel detector in an SOI technology are explained.

Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s employing silicon substrate with a thin epitaxial layer in which deposited charge is collected by disordered diffusion rather than by drift in an electric field. As a consequence the signal is small and slow, and the radiation tolerance is below the requirements for LHC experiments by factors of 100 to 1000. We developed fully depleted (D)MAPS pixel sensors employing a 150 nm CMOS technology and using a high resistivity substrate as well as a high biasing voltage. The development has been carried out in three subsequent iterations, from prototypes to a large pixel matrix comprising a complete readout architecture suitable for LHC operation. Full CMOS electronics is embedded in large deep n-wells which at the same time serve as collection nodes (large electrode design). The devices have been intensively characterized before and after irradiation employing lab tests as well as particle beams. The devices can cope with particle rates seen by the innermost pixel detectors of the LHC pp-experiments or as seen by the outer pixel layers of the planned HL-LHC upgrade. They are radiation hard to particle fluences of at least 1015 neq/cm2 and total ionization doses of at least 50 Mrad. Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s employing silicon substrate with a thin epitaxial layer in which deposited charge is collected by disordered diffusion rather than by drift in an electric field. As a consequence the signal is small and slow, and the radiation tolerance is below the requirements for LHC experiments by factors of 100 to 1000. We developed fully depleted (D)MAPS pixel sensors employing a 150 nm CMOS technology and using a high resistivity substrate as well as a high biasing voltage. The development has been carried out in three subsequent iterations, from prototypes to a large pixel matrix comprising a complete readout architecture suitable for LHC operation. Full CMOS electronics is embedded in large deep n-wells which at the same time serve as collection nodes (large electrode design). The devices have been intensively characterized before and after irradiation employing lab tests as well as particle beams. The devices can cope with particle rates seen by the innermost pixel detectors of the LHC pp-experiments or as seen by the outer pixel layers of the planned HL-LHC upgrade. They are radiation hard to particle fluences of at least $10^{15}~\mathrm{n_{eq}/cm^2}$ and total ionization doses of at least 50 Mrad.

International audience; A major upgrade for the ATLAS Inner Tracker at the Large Hadron Collider (LHC) is scheduled in 2026. Depleted CMOS pixel sensors on high resistivity substrates in LFoundry 150 nm technology are an interesting option for this upgrade. Recently two large demonstrators, one based on a hybrid concept called LF-CPIX and the other based on a fully monolithic concept called LF-Monopix have been produced. Both prototypes were characterized in the lab and after irradiation up to 160 MRad under CERN’s 24 GeV Proton Synchrotron beam. In this work, we will describe the behavior under radiation of the two prototypes.

International audience; High Voltage CMOS (HVCMOS) sensor is a proposed cost effective alternative to the existing hybrid sensors in ATLAS ITk pixel barrel for outer layers. To prove the feasibility of HVCMOS sensors in ATLAS experiment, a large area demonstrator chip is being designed. This work presents the design details of three HVCMOS sensor chips with an overview of the measurement results of ATLASpix1 which is the first large area (1 cm × 2 cm) prototype in 0.18 μ m process.

Depleted Monolithic Active Pixel Sensors (DMAPS) constitute a promising low cost alternative for the outer layers of the ATLAS experiment Inner Tracker (ITk). Realizations in modern, high resistivity CMOS technologies enhance their radiation tolerance by achieving substantial depletion of the sensing volume. Two DMAPS prototypes that use the same “column-drain” readout architecture and are based on different sensor implementation concepts named LF-Monopix and TJ-Monopix have been developed for the High Luminosity upgrade of the Large Hadron Collider (HL-LHC). Depleted Monolithic Active Pixel Sensors (DMAPS) constitute a promising low cost alternative for the outer layers of the ATLAS experiment Inner Tracker (ITk). Realizations in modern, high resistivity CMOS technologies enhance their radiation tolerance by achieving substantial depletion of the sensing volume. Two DMAPS prototypes that use the same "column-drain" readout architecture and are based on different sensor implementation concepts named LF-Monopix and TJ-Monopix have been developed for the High Luminosity upgrade of the Large Hardon Collider (HL-LHC). LF-Monopix was fabricated in the LFoundry 150 nm technology and features pixel size of $50x250~\mu m^{2}$ and large collection electrode opted for high radiation tolerance. Detection efficiency up to 99\% has been measured after irradiation to $1\cdot10^{15}~n_{eq}/cm^{2}$. TJ-Monopix is a large scale $(1x2~cm^{2})$ prototype featuring pixels of $36x40~\mu m^{2}$ size. It was fabricated in a novel TowerJazz 180 nm modified process that enables full depletion of the sensitive layer, while employing a small collection electrode that is less sensitive to crosstalk. The resulting small sensor capacitance ($

International audience; A practical, yet physically grounded, TCAD modeling approach to study the radiation damage effects on silicon detectors exposed to the very high fluences expected at High Luminosity LHC (greater than 2.2×10 16 1MeV n eq /cm 2 ) is presented in this work. The modeling strategy is based on combined bulk and surface damage effects accounting for a limited number of measurable parameters. Starting from standard test structure measurements (i.e. MOS capacitors, gated diodes and MOSFETs), the most relevant parameters able to describe the complex phenomena related to the damage effects at these very high fluences have been extracted and therefore fed as input to the simulation tools. In particular the properties of the SiO 2 layer and of the SiO 2 /Si interface have been deeply investigated on high-resistivity n-type and p-type silicon test structures, before and after irradiation with X-rays in the range from 50 krad(SiO 2 ) to 20 Mrad(SiO 2 ). Thus the extrapolated dose-dependent parameters (e.g. interface trap density and oxide charge density) have been straight included in the TCAD modeling scheme. The adopted numerical approach has been validated by means of the comparison between simulation results and experimental data. To this purpose, steady-state and small signal analysis have been selected as reference analyses to assess the model suitability along with the charge collection efficiency. Different technology and design options/detector geometries can be therefore evaluated, from conventional planar pixelated (strip/pixel) detectors to active-edges or 3D (columnar electrodes) detectors, as well different principle of operation such as charge multiplication in Low Gain Avalanche Detector. This would support technology independence of the model and its use as a predictive tool for the design and the optimization of new classes of silicon sensors for the next generation High-Energy Physics experiments.

Depleted monolithic CMOS 1 1 Complementary metal-oxide-semiconductor. active pixel sensors (DMAPS) have been developed to demonstrate their suitability as pixel detectors in the outer layers of the ATLAS Inner Tracker (ITk) pixel detector in the High-Luminosity Large Hadron Collider (HL-LHC). Two prototypes have been fabricated using a 150 nm CMOS technology on high resistivity ( ≥ 2 k Ω cm) wafers. The chip size of 10 mm × 10 mm is similar to that of the current FE-I3 ATLAS pixel detector readout chip. One of the prototypes is used for detailed characterization of the sensor and analog front end circuitry of the DMAPS. The other one is a fully monolithic DMAPS, including fast readout digital logics that handle the required hit rate. To yield a strong homogeneous electric field within the sensor volume, back-side process of the wafer was tested. The prototypes were irradiated with X-rays up to a total ionization dose (TID) of 50 Mrad(SiO 2 ) and with neutrons up to a 1 MeV neutron equivalent fluence of 10 15 n eq /cm 2 to test non-ionizing energy loss (NIEL) effects. The analog front end circuitry maintained its performance after TID irradiation, and the hit efficiency at < 10 −7 noise occupancy was as high as 98.9% after NIEL irradiation. Depleted monolithic CMOS active pixel sensors (DMAPS) have been developed in order to demonstrate their suitability as pixel detectors in the outer layers of a toroidal LHC apparatus inner tracker (ATLAS ITk) pixel detector in the high-luminosity large hadron collider (HL-LHC). Two prototypes have been fabricated using 150 nm CMOS technology on high resistivity (> 2 k$\Omega$ $cm^2$) wafers. The chip size is equivalent to that of the current ATLAS pixel detector readout chip. One of the prototypes is used for detailed characterization of the sensor and the analog readout of the DMAPS. The other is a fully monolithic DMAPS including fast readout digital logic that handles the required hit rate. In order to yield a strong homogeneous electric field within the sensor volume, thinning of the wafer was tested. The prototypes were irradiated with X-ray up to a total ionization dose (TID) of 50 Mrad and with neutrons up to non-ionizing energy loss (NIEL) of $10^{15}$ $n_{eq}/cm^2$. The analog readout circuitry maintained its performance after TID irradiation, and the hit-efficiency at > $10^7$ noise occupancy was as high as 98.9 % after NIEL irradiation.

The expected increase of the particle flux at the high luminosity phase of the LHC with instantaneous luminosities up to L ≃ 7.5 × 10^{34} cm^{−2} s^{−1} will have a severe impact on pile-up. The pile-up is expected to increase on average to 200 interactions per bunch crossing. The reconstruction and trigger performance for especially jets and transverse missing energy will be severely degraded in the end-cap and forward region. A High Granularity Timing Detector (HGTD) is proposed in front of the liquid Argon end-cap calorimeters for pile-up mitigation at Level-0 (L0) trigger level and in the offline reconstruction. This device cover the pseudo-rapidity range of 2.4 to about 4.2. Four layers of Silicon sensors, possibly interleaved with Tungsten, are foreseen to provide precision timing information for charged and neutral particles with a time resolution of the order of 30 pico-seconds per readout cell in order to assign the energy deposits in the calorimeter to different proton-proton collision vertices. Each readout cell has a transverse size of only a few mm, leading to a highly granular detector with several hundred thousand readout cells. The expected improvements in performance are relevant for physics processes, i.e, vector-boson fusion and vector-boson scattering processes, and for physics signatures with large missing transverse energy. Silicon sensor technologies under investigation are Low Gain Avalanche Detectors (LGAD), pin diodes, and HV-CMOS sensors. In this presentation, starting from the physics motivations and expected performance of the High Granular Timing Detector, the proposed detector layout and Front End readout, laboratory and beam test characterization of sensors and the results of radiation tests will be discussed.

International audience; A HV/HR CMOS detector prototype called LF-CPIX, has been designed in LFoundry 150nm technology. The front-end electronics has been implemented using both NMOS and PMOS transistors, inside the charge collection diode, with a pitch of 250 μm × 50 μm. This demonstrator is an implementation of a matrix of smart pixels where the diode is composed by a Deep Nwell, and P-type substrate is used as a depleted sensor. Three types of pixels have been developed: passive pixels, analog-digital pixels, analog pixels. The analog pixels can be connected to the FE-I4 IC, which is the present readout IC of the innermost ATLAS pixel layers. The different versions of the LF-CPIX demonstrators are described, characterization of the different pre-amplifiers flavors with external injection signal and55Fe source are presented for the digital pixels. Finally radiation hardness results are discussed.

To cope with the harsh environment foreseen at the high luminosity conditions of HL- LHC, the ATLAS pixel detector has to be upgraded to be fully efficient with a good granularity, a maximized geometrical acceptance and an high read out rate. LPNHE, FBK and INFN are involved in the development of thin and edgeless planar pixel sensors in which the insensitive area at the border of the sensor is minimized thanks to the active edge technology. In this paper we report on two productions, a first one consisting of 200 {\mu}m thick n-on-p sensors with active edge, a second one composed of 100 and 130 {\mu}m thick n-on-p sensors. Those sensors have been tested on beam, both at CERN-SPS and at DESY and their performance before and after irradiation will be presented., Comment: 10 pages, 7 figures, to appear in the proceedings of the PSD11 conference, 3th-8th September 2017, Open University (Milton Keynes)

International audience; This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150 nm CMOS process. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade for the High Luminosity Large Hadron Collider (HL-LHC). Implementing such a device in the detector module will result in a lower production cost and lower material budget compared to the presently used hybrid designs. In this paper the chip architecture will be described followed by the simulation and measurement results.

Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. Depleted fully monolithic CMOS pixels with fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-MonoPix and TJ-MonoPix, are presented. LF-MonoPix was designed and fabricated in the LFoundry 150~nm CMOS technology, and TJ-MonoPix has been designed in the TowerJazz 180~nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The design of the two prototypes will be described. First measurement results for LF-MonoPix will also be shown., International Workshop on Radiation Imaging Detectors 2017

To cope with the High Luminosity LHC harsh conditions, the ATLAS inner tracker has to be upgraded to meet requirements in terms of radiation hardness, pile up and geometrical acceptance. The active edge technology allows to reduce the insensitive area at the border of the sensor thanks to an ion etched trench which avoids the crystal damage produced by the standard mechanical dicing process. Thin planar n-on-p pixel sensors with active edge have been designed and produced by LPNHE and FBK foundry. Two detector module prototypes, consisting of pixel sensors connected to FE-I4B readout chips, have been tested with beams at CERN and DESY. In this paper the performance of these modules are reported. In particular the lateral extension of the detection volume, beyond the pixel region, is investigated and the results show high hit-efficiency also at the detector edge, even in presence of guard rings., 14 pages, 11 figures

The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results. The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

Nuclear instruments & methods in physics research / A 831, 189 - 196(2016). doi:10.1016/j.nima.2016.05.092, ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation., Published by North-Holland Publ. Co., Amsterdam

In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of novel n-on-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology an overview of the first beam test results will be given., 4 pages, 9 figures, conference record of 2015 IEEE NSS, San Diego (CA), 31/10-7/11/2015

The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS., 4 pages, 4 figures, VCI 2016 conference proceedings

International audience; The entire ATLAS inner tracking system will be replaced for operation at the HL-LHC . This will include a significantly larger pixel detector of approximately 15 m(2). For this project, it is critical to reduce the mass of the hybrid pixel modules and this requires thinning both the sensor and readout chips to about 150 micrometres each. The thinning of the silicon chips leads to low bump yield for SnAg bumps due to bad co-planarity of the two chips at the solder reflow stage creating dead zones within the pixel array. In the case of the ATLAS FEI4 pixel readout chip thinned to 100 micrometres, the chip is concave, with the front side in compression, with a bow of +100 micrometres at room temperature which varies to a bow of −175 micrometres at the SnAg solder reflow temperature, caused by the CTE mismatch between the materials in the CMOS stack and the silicon substrate. A new wafer level process to address the issue of low bump yield be controlling the chip bow has been developed. A back-side dielectric and metal stack of SiN and Al:Si has been deposited on the readout chip wafer to dynamically compensate the stress of the front side stack. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach which is under development for this chip. It is demonstrated that the amplitude of the correction can be manipulated by the deposition conditions and thickness of the SiN/Al:Si stack. The bow magnitude over the temperature range for the best sample to date is reduced by almost a factor of 4 and the sign of the bow (shape of the die) remains constant. Further development of the backside deposition conditions is on-going with the target of close to zero bow at the solder reflow temperature and a minimal bow magnitude throughout the temperature range. Assemblies produced from FEI4 readout wafers thinned to 100 micrometres with the backside compensation layer have been made for the first time and demonstrate bond yields close to 100%.